初创公司尽调
尽调报告 Robotics / Hardware / AI Semiconductor Series A 2026-06-13

Ricursive Intelligence

AlphaChip 背景和融资速度都很突出,但商业验证仍大多停留在私域

Ricursive 兼具罕见的 AlphaChip 技术信誉和惊人的融资速度,但公开客户、收入和基准测试证据仍不足,无法完整承销 $4B 估值。

封面要素

公司概况

Ricursive Intelligence 是一家位于 Palo Alto 的私人前沿 AI 实验室,由 AlphaChip 背后的研究人员 Anna Goldie 和 Azalia Mirhoseini 于 2025 年底创立。公司在打造 AI 驱动的半导体设计平台,目标是压缩芯片开发周期,并让 AI 模型与定制硅片更紧密地共同演进。公开证据显示,创始人与市场匹配度异常高,投资人需求也很强,但公司尚未披露投资人承销一家 $4 billion 软件和基础设施公司通常需要的经营指标。

官网
www.ricursive.com
成立时间
2025-12-02
创始人
Anna Goldie, Azalia Mirhoseini
创立地点
Palo Alto, California, USA
总部
Palo Alto, California, USA
产品
面向半导体设计自动化的 AI 软件平台,覆盖布局、优化、验证和更广泛的全栈工作流迭代;Ricursive 本身不制造芯片。
客户
前沿 AI 实验室、超大规模云厂商、大型无晶圆厂半导体公司,以及推进定制硅片的系统公司。
商业模式
可能是企业软件 / 平台授权,加上面向芯片设计团队的高接触工作流集成;具体定价和变现方式仍未公开披露。
阶段
Series A
融资情况
2025 年 12 月以 $750M 估值完成 $35M 种子轮,2026 年 1 月以 $4B 投后估值完成 $300M Series A 轮,已披露累计融资 $335M。
[CO001, CO006, CO008, CO009, CE004, CE017, CU011, CI040]

执行摘要

主要优势

  • 创始人 Anna Goldie 和 Azalia Mirhoseini 是 AlphaChip 共同创造者,在 AI 驱动芯片设计上已有生产相关研究,品类权威性少见。
  • Ricursive 打的是战略瓶颈:定制硅需求上升,但芯片设计周期仍长、贵,单靠人工流程很难扩展。
  • 公司在启动约两个月内披露融资 $335M,其中包括 Lightspeed 领投的 $300M Series A,以及 NVentures 等战略投资人参与。

主要风险

  • 公开证据仍未披露具名 Ricursive 客户、收入、定价、留存或毛利结构,商业耐久性很难承销。
  • 既有 EDA 厂商 Synopsys 和 Cadence 已把 AI 辅助工具嵌进深度绑定的客户工作流,Ricursive 必须证明端到端优势,而不只是技术野心。
  • $4B 估值看起来主要由创始人稀缺性和战略叙事驱动,早于公开经营证据;如果基准测试、采用或变现滞后,下行空间很大。

未决问题

  • 没有公开收入、年经常性收入(ARR)、毛利率、烧钱速度、现金余额或现金跑道披露。
  • 公开来源仍未确认具名付费客户、量产设计 wins、留存、NPS 或客户集中度。
  • 针对 Synopsys DSO.ai、Cadence Cerebrus 或其他既有流程的外部基准测试,公开记录仍有限。
  • 治理深度、董事会构成,以及 January 2026 Series A 内嵌的权利,公开层面仍未披露。

目录

Chapter 01

01公司概况

1.1 身份、产品与阶段

Ricursive Intelligence 于 2025 年 12 月 2 日公开亮相,是一家专注用 AI 加速半导体设计的前沿 AI 实验室。公司官网和发布材料把它描述为在搭建自我改进系统:先从芯片设计切入,再把更好的模型和更好的硅片连成递归闭环。它的产品主张不只是单点 EDA 工具;保留来源描述的是一个跨半导体设计栈优化版图、验证和架构探索的平台。TechCrunch 也报道称,Ricursive 在打造设计芯片的 AI 工具,而不是自己制造芯片;这会影响后续尽调判断其商业模式、资本强度和潜在客户基础。 公开地点证据指向 California 的 Palo Alto,而不是分布式多办公室。独立报道称 Ricursive 总部在 Palo Alto,当前 Ashby 招聘页也把所有开放岗位列为 Palo Alto 现场办公。截至 2026-06-13 的运行日期,Ricursive 仍更适合被理解为一家刚推出的私人 Series A 公司:它很快融到异常大额资金,但保留的公开来源没有具名客户、披露收入,也没有给出客户数指标。这个缺口让本章更侧重身份、资本和创始人质量分析,而不是常规牵引力承销。[CO001, CO002, CO003, CO004, CO005, CO006]

快照 KPI 表
指标数值 / 状态日期置信度缺口
创立 / 公开发布锚点2025-12-02 公开发布;法律注册日期未公开披露2025-12-02需要公司设立文件或法律实体备案来确认注册日期
总部 / 运营基地Palo Alto, California2026-06-13保留官方来源未发布正式注册地址或总部地址
公司阶段私有 Series A 前沿 AI 实验室2026-06-13
产品 / 商业模式面向芯片厂商和电子团队销售的半导体设计 AI 平台;不是芯片制造商2026-02-16商业包装和定价未公开披露
最新估值(USD B)4.0 投后2026-01-26
累计融资(USD M)3352026-02-16累计融资依赖公司网站和 TechCrunch 摘要,而非股权结构表披露
已披露具名客户02026-06-13保留公开来源没有点名付费客户或设计胜利
收入 / 运行率 / ARR私营公司;保留来源中无公开收入指标
员工数唯一招聘代理是 7 个开放职位;没有全公司员工数披露
公开证明的工作地点1(仅 Palo Alto 现场职位)2026-06-13保留来源未公开记录国际办公室足迹
监管暴露通过美国 AI 芯片出口管制和伙伴合规形成间接暴露2026-06-13需要法律顾问审查终端市场、客户和算力伙伴限制

快照指标强调公开来源能支持什么、不能支持什么。融资和估值证据充分;客户、收入、员工数和法律实体细节仍为私有或未披露。

[CO001, CO006, CO007, CO008, CO009, CO011]
FO002: 公司快照逻辑

Ricursive 当前阶段的创始人谱系、平台、买方、资本和依赖如何连接。

[CO002, CO003, CO008, CO009, CO020, CO021]
FO003: 快照 KPI

可由公开信息支撑的指标,用于概括 Ricursive 的成熟度和最重要披露缺口。

客户和高管人数反映的是公开披露,不代表内部真实情况。估值跃升只是用已披露种子轮和 Series A 估值做的简单计算。

[CO004, CO005, CO008, CO009, CO011, CO022]

1.2 创始人、领导层、治理与关键人依赖

Ricursive 目前的可投资性很大程度压在两个人身上:联合创始人兼 CEO Anna Goldie,以及联合创始人兼 CTO Azalia Mirhoseini。两人与市场的匹配度异常强,因为公司正在直接商业化她们多年研究 AI 辅助芯片设计时共同发展出的投资逻辑。Nature 2021 年的 AlphaChip 论文确立了技术传承;Sequoia 的播客提到 AlphaChip 将布图规划从数月压缩到数小时;Google Research 的 circuit_training 仓库称该框架为开源,并已在 Alphabet 内外使用。结果是一个少见案例:公司的起源故事、技术方法和招聘叙事都指向同一种核心能力。 不过,公开记录并非完全干净。多个与 Ricursive 相关的来源称 AlphaChip 影响了四代 TPU,而 New Scientist 2024 年的批评称 Google DeepMind 描述的是三代 TPU,并引用专家观点,认为“超人类”性能的公开证据仍不足。这不会击穿投资逻辑,但意味着创始叙事应被视为可信但有争议,而不是既成事实。治理披露也很薄:保留的公开来源一致确认两位创始人分别担任 CEO 和 CTO,但没有公布董事会名单或更完整的高管目录。因此,Ricursive 面临集中的关键人风险,外部也很难看清创始二人之外的管理层深度。[CO004, CO005, CO012, CO013, CO014, CO015]

领导层和创始人表
人物角色背景 / 职能覆盖创始人与市场匹配关键人物依赖
Anna Goldie联合创始人兼 CEO前 Google 研究员,与 AlphaChip 传承相关;Ricursive 递归 AI 硬件投资逻辑的公开面孔正在把她在发布前研究过的技术问题商业化在融资、战略和企业可信度上的最高外部依赖
Azalia Mirhoseini联合创始人兼 CTO前 Google 研究员、AlphaChip 共同创建者;模型硬件协同设计和平台范围的技术负责人对芯片设计 RL 方法和全栈技术路线图拥有深度领域主导权平台可信度、招聘和差异化上的最高技术依赖

保留公开来源一致披露两位创始人及其角色,但没有提供公开董事会名单或更广泛的高管目录。因此,本表捕捉的是全部公开具名领导层,而不是完整内部组织结构图。

[CO004, CO005, CO012, CO013, CO016, CO017]

1.3 资本基础、投资人图谱与规模指标

Ricursive 的融资速度是公司概况里最醒目的一项事实。公司于 2025-12-02 以 $750 million 估值完成 $35 million 种子轮并公开亮相,随后在 2026-01-26 宣布以 $4 billion 投后估值完成 $300 million Series A 轮。TechCrunch 后来汇总其累计融资为 $335 million,Ricursive 官网也重复这一数字,并列出 Sequoia、Lightspeed、DST 和 NVentures 等支持方。按简单算术,估值在不到两个月内从种子轮到 Series A 大约上涨 5.3x;即便按 2026 年前沿 AI 标准看,这也很异常。 投资人组合和融资金额同样重要。Sequoia 领投种子轮,Lightspeed 领投 Series A。公司和独立媒体还点名 DST Global、NVentures、Felicis、49 Palms、Radical 等。投资人文章显示,本轮融资至少同样受创始人履历和硬件-软件协同设计投资逻辑驱动,而不只是已披露商业牵引力。公开规模信号仍偏早期而非成熟:官网称 Ricursive 正在扩张一支小而精的团队,招聘页显示七个现场开放岗位,覆盖核心产品、基础设施、研究和安全。保留的融资来源均未披露债务、收入或股权结构表拆分,因此后续章节应把当前资本化状态视为资金充足,但结构上仍不透明。[CO001, CO008, CO009, CO010, CO022, CO023]

利益相关方或投资人图谱
利益相关方角色 / 持股类型公开证明的参与控制 / 经济重要性尽调要求
Sequoia Capital种子轮领投方2025-12-02 种子轮;Series A 财团中仍被点名最早的机构支持者;可能在创始人招聘和治理搭建中有影响力确认董事席位、pro-rata 权利,以及 Series A 后当前持股
Lightspeed Venture PartnersSeries A 领投方2026-01-26 领投 $300M Series A可能是当前优先股堆叠中的锚定投资人,也是 $4B 标记的主要外部背书方确认董事会权利、清算优先权和集中度风险
DST Global成长轮投资人在 Series A 财团和 Ricursive 网站支持者名单中被点名全球成长资本支持的重要信号确认支票规模、持股,以及任何地理扩张影响
NVentures战略企业风险投资人在 Series A 财团和 Ricursive 网站支持者名单中被点名把 Ricursive 连接到 NVIDIA 生态,但不等于披露 NVIDIA 是客户澄清信息权、战略限制,以及与非 NVIDIA 芯片厂商客户的冲突处理
FelicisSeries A 参与方公开宣布参与,并与创始人有长期关系关系驱动型投资人,了解创始人的公司前合作确认持股,以及任何创始人服务或人才网络角色
49 Palms VenturesSeries A 参与方在公司和媒体对 Series A 的报道中被点名额外资本支持,但公开战略角色未披露确认经济条款、权利,以及参与是直接还是通过 SPV 结构
Radical VenturesSeries A 参与方在公司和媒体对 Series A 的报道中被点名强化前沿 AI 投资人对公司的兴趣确认持股、AI 治理预期和后续轮次支持意愿

这张图谱捕捉公开具名的种子轮和 Series A 利益相关方。准确持股、董事席位、优先股堆叠、老股交易和任何 side-letter 经济条款,保留公开材料均未披露。

[CO001, CO008, CO009, CO010, CO023, CO024]

1.4 里程碑、生态依赖与反向证据

Ricursive 公司年轻,里程碑记录不长,但信息密度很高。公司成立前最重要的里程碑,是创始人在 2018 年围绕 AI 驱动芯片设计展开合作,以及 2021 年 AlphaChip 论文发表;二者共同构成创始人合法性的证据基础。公司里程碑随后快速推进:2025 年 12 月公开亮相并完成种子轮融资,2026 年 1 月完成大额 Series A,2026 年 6 月的招聘足迹仍围绕 Palo Alto 一个办公室展开。产品叙事也从布图规划传承扩展为更广泛的全栈设计平台;TechCrunch 报道的工作流从组件放置一直延伸到设计验证。 主要风险在外部依赖和证明不透明。Ricursive 并不孤独:Synopsys DSO.ai 和 Cadence Cerebrus 表明,AI 辅助芯片设计已经是商业品类,所以公司必须证明全栈差异化,而不只是“EDA 里的 AI”。与此同时,Google TPU、AWS Trainium 和 Microsoft Maia 证明超大规模云厂商对定制硅片有真实需求,这有助于解释投资人热情。监管敞口是间接但仍重要的,因为 BIS、CSIS 和 Morrison Foerster 都显示,先进计算和 AI 芯片生态仍受不断变化的美国出口管制和执法规则约束。最后,New Scientist 的批评和缺少具名设计胜利意味着,Ricursive 的技术投资逻辑有吸引力,但外部尚未定论。[CO014, CO018, CO019, CO020, CO030, CO031]

里程碑表
日期事件类型金额 / 估值 / 状态参与方含义
2018Goldie 和 Mirhoseini 开始共同探索芯片设计投资逻辑创立公司前合作开始Anna Goldie; Azalia Mirhoseini建立公司创始人与市场匹配背后的长期前史
2021Nature 发表 AlphaChip 论文产品RL 布图规划方法发表Goldie; Mirhoseini; Google 合作者; Nature形成后来支撑 Ricursive 可信度的技术传承
2024-10-02New Scientist 发表对 AlphaChip 优势主张的批评反向外部质疑已有记录New Scientist; 独立芯片设计研究人员显示创始技术逻辑在公司相关来源之外仍有争议
2025-05-13BIS 发布影响先进计算芯片和 AI 模型训练的管制政策声明监管美国政策澄清Bureau of Industry and Security(美国工业与安全局)为 Ricursive 可能服务的 AI 芯片生态建立监管依赖
2025-12-02Ricursive 公开发布,并宣布由 Sequoia 领投的 $35M 种子轮创立$35M 种子轮;$750M 估值Ricursive; Sequoia Capital把研究逻辑变成获得融资的运营公司
2025-12-02发布材料描述了一个面向半导体设计的全栈平台,以及早期企业 / 超大规模客户推进伙伴关系产品和商业化范围公布Ricursive; 未具名企业和超大规模云交易对方显示公司野心不止于狭窄的布图规划工具,但没有具名设计胜利
2026-01-26Ricursive 宣布由 Lightspeed 领投的 $300M Series A融资$300M Series A;$4B 投后估值Lightspeed; DST Global; NVentures; Felicis; 49 Palms; Radical; Sequoia; 其他确认异常快速的资本形成速度和投资人信念
2026-02-16TechCrunch 报道累计融资 $335M,并把芯片制造商 / 电子公司识别为目标客户规模据报道累计融资 $335MTechCrunch; Ricursive 创始人将公司重新定位为面向芯片生态的设计平台供应商,而不是直接芯片生产商
2026-06-13Ashby 列出 7 个 Palo Alto 现场开放职位,覆盖 EDA、基础设施、研究和安全治理7 个开放职位Ricursive 招聘团队显示团队正在扩建、集中于一个办公室,公开管理层足迹仍薄

里程碑包括公司事件,也包括理解 Ricursive 可信度所需的最重要公司前传承事件。保留公开来源没有披露这些项目之外的具名商业设计胜利、董事会变动或客户发布。

[CO001, CO008, CO012, CO014, CO016, CO021]
FO001: 公司里程碑时间线

从 2018 年公司成立前的投资逻辑,到 Ricursive 2026 年 6 月的招聘足迹,串起创始人谱系和公司里程碑。

保留的全文摘录没有在清晰页眉中显示 Nature 论文发布日期,因此时间按年份粒度展示。时间线有意纳入公司成立前谱系,因为这段历史是 Ricursive 创始人市场匹配的核心。

[CO001, CO008, CO012, CO014, CO016, CO021]

1.5 图表

Chapter 02

02市场分析

2.1 市场边界、纳入支出与替代方案

Ricursive 应被分析为 AI 芯片设计自动化平台,而不是半导体制造商、晶圆厂、晶圆厂设备供应商或 AI 芯片卖家。公司官网、发布材料和独立报道都把它放在软件层:帮助工程师更快创造定制硅片。这一区分很重要,因为前沿 AI 投资很容易借用 AI 加速器收入、晶圆代工收入或晶圆厂设备资本开支等巨大相邻数字,并称之为 TAM。这些资金池是需求驱动因素或背景,但不是 Ricursive 销售进入的市场。 最相关的纳入支出,是改善芯片设计工作流的软件和服务:布图规划、PPA 优化、设计收敛、验证辅助,以及在公司证明能超越版图之后可能延伸到的架构探索。现状替代方案仍是劳动密集型的既有 EDA 流程,工程团队在成熟工具里手工迭代直到收敛。最近的相邻替代品,是 Synopsys 和 Cadence 已经销售的 AI 模块。这些既有厂商证明品类存在,但也收窄了边界:Ricursive 可信的市场是芯片设计内部的自动化层,而不是整个半导体价值链。[CM001, CM002, CM003, CM004, CM005, CM006]

市场定义表
细分 / 类别纳入支出排除支出买家 / 付款方相关性
广义 EDA 和 IP 软件池仅作为通过现有厂商收入估算的软件上限晶圆代工服务、掩模、制造、晶圆厂设备半导体设计组织中的 CAD / 硅工程预算最相关的广义背景,因为 Ricursive 卖进软件工作流,而不是硬件资本开支
AI PPA / 布图规划自动化用于布局、PPA 搜索和流程优化模块的点状工具支出与芯片设计无关的通用 ML 工具物理设计和 CAD 团队直接相关,因为公开的现有厂商证明今天在这里最强
全栈 AI 芯片设计自动化从布局向验证、设计收敛和更广泛平台编排延伸的工作流自动化成品芯片、晶圆产出、晶圆代工产能硅平台和工程负责人这是 Ricursive 的核心投资逻辑;如果证明成立,也是它可能捕获的最大软件层
定制硅项目设计预算绑定战略 ASIC 或加速器项目的自动化叠加层和增量软件 / 服务支出流片制造成本和云推理收入超大规模云厂商、无晶圆厂或 OEM 芯片项目负责人定义可能的近期可服务市场,其中速度 ROI 最高
晶圆厂设备和晶圆代工资本开支None晶圆厂工具、工艺设备、封装线、晶圆代工收入半导体制造商和晶圆代工厂重要需求背景,但不是 Ricursive TAM
AI 加速器销售和云 AI 收入NoneGPU、TPU、Trainium、Maia、云服务收入云和平台业务单元下游需求信号,不是 Ricursive 开票的软件市场

这里必须守住边界:纳入支出仅限芯片设计软件和相邻自动化服务。来自 AI 加速器、晶圆厂设备或晶圆代工的大额硬件数字被明确排除在 Ricursive TAM 之外,尽管它们会强化定制硅项目的紧迫性。

[CM001, CM004, CM015, CM021, CM029, CM030]
FM001: 市场规模测算视角

三层规模框架,从宽口径在位设计软件天花板,到 Ricursive 的近期滩头市场。

中层和底层是分析师估计,锚定在可观测的 Synopsys 加 Cadence 收入天花板之下;它们明确不是由晶圆厂设备或 AI 芯片收入池推导而来。

[CM022, CM024, CM027, CM039]

2.2 多重市场规模视角与相互矛盾的估算

最好的测算纪律,是先找一个可观察的宽口径天花板,再向下收敛。广义 EDA 和 IP 软件池最干净的上限代理是既有厂商收入:CompaniesMarketCap 报告 Synopsys 2025 年收入约 8.00 billion dollars,Cadence 为 5.29 billion dollars,合计约 13.29 billion dollars;2026 年过去十二个月池子也类似,为 13.52 billion dollar。这个视角仍不完美,因为这些收入包含 Ricursive 尚未替代的传统流程、IP 和企业关系。但它远比借用半导体资本开支或 AI 芯片收入更站得住。 第二个视角是下游紧迫性。SEMI 预测 2025 年晶圆厂设备支出为 110 billion dollars,2026 年为 130 billion dollars,说明 AI 相关芯片需求正在沿硬件栈推动资本形成。不过,这不能一比一转化为 Ricursive 的软件 TAM。需要保留的矛盾是:围绕定制硅片的风投叙事在紧迫性方向上是对的,但当前已经变现的软件控制点远小于相邻硬件资金池。因此,这里的窄口径市场估算采用锚定既有厂商软件天花板的低 / 基准 / 高区间,而不是锚定半导体总支出。[CM020, CM021, CM022, CM023, CM024, CM025]

TAM / SAM / SOM 规模测算视角表
发布方 / 视角年份地理范围数值CAGR / 增长方法置信度局限
CompaniesMarketCap / Synopsys 收入2025全球USD 8.00B31.9% YoY vs 2024用可观察的现有厂商收入代理广义 EDA/IP 软件需求包含传统软件和 IP,不只是 AI 自动化
CompaniesMarketCap / Cadence 收入2025全球USD 5.29B14.1% YoY vs 2024用可观察的现有厂商收入代理广义 EDA/IP 软件需求包含传统软件和服务,不只是 AI 自动化
分析师综合 / 广义软件上限2025-2026全球USD 13.29B-13.52B低双位数增长Synopsys 和 Cadence 收入之和;用作广义设计软件控制点的外层上限仍宽于 Ricursive 可能服务的市场,也不是直接 Ricursive TAM
SEMI / 晶圆厂设备背景2025全球USD 110B+2% YoYWorld Fab Forecast 给出的前端晶圆厂设备支出预测相邻硬件 capex,不是软件 TAM
SEMI / 晶圆厂设备背景2026 预测全球USD 130B+18% YoY前瞻 capex 信号,显示 AI/HPC 驱动的硬件栈紧迫性只可作为需求驱动因素,不是 Ricursive 收入池
分析师综合 / 狭义 AI 自动化 SAM2026 当前状态全球USD 2.0B-5.0Bn/a假设广义 EDA 支出中只有一部分会在最先进定制硅项目中迁移到多阶段 AI 自动化需要证明其能扩展到公开布图规划 / PPA 证据之外
分析师综合 / 近期滩头 SOM2026 当前状态全球USD 0.5B-1.5Bn/a假设早期捕获集中在痛点最高设计团队的块级和点状工具式自动化取决于信任、试点转化和预算归属,这些尚未公开

本表刻意使用多个视角。广义上限来自现有厂商软件收入,狭义 SAM 和滩头 SOM 则是分析师估计,明确低于该上限,并避免把半导体 capex 当作软件 TAM。

[CM020, CM021, CM022, CM023, CM025, CM026]
FM002: 市场估计区间

AI 芯片设计自动化三个范围的低 / 基准 / 高年度支出区间,单位均为 USD billions。

低 / 基准 / 高数值都是年度软件支出估计,单位为 USD billions。最上行假设 AI 仍然窄、以点工具为主;中间行假设先进定制硅团队更广泛采用多阶段自动化;底行使用 2024-2026 年 Synopsys 加 Cadence 收入作为外层天花板,而不是现实的近期 SAM。

[CM023, CM026, CM027, CM028]

2.3 买方分层、预算归属与采用路径

公开证据显示,Ricursive 最早的买方不是所有地方的所有芯片用户,而是那些时间压缩价值数百万美元、且定制硅片已经具有战略意义的组织。TechCrunch 称,任何制造电子产品且需要芯片的公司都在范围内,但现实中的第一波会更窄:超大规模云厂商的硅片团队、先进制程无晶圆厂芯片设计商,以及打造定制 ASIC 的系统公司。这些买方已经长期承受漫长设计周期、昂贵工程团队,以及靠定制硅片形成差异化的上升压力。 用户群比买方集合更具体。物理设计、CAD 和验证团队会先评估产品,因为 Synopsys 和 Cadence 的既有厂商案例仍扎根于 PPA 和流程优化。预算权力可能从这些团队开始,一旦工具触及多个工作流阶段或企业级算力承诺,再向上扩展。因此,采用路径应被理解为分阶段信任曲线:基准测试可信度、在一个模块上试点、延伸到验证或签核,然后才是项目级标准化。这个顺序让 Ricursive 近期 SOM 比其宏大叙事更窄。[CM003, CM005, CM006, CM007, CM015, CM031]

细分 / 买家图谱
细分买家用户付款方工作流预算所有者采用触发因素
超大规模云厂商芯片团队芯片或平台工程负责人物理设计、CAD 与验证工程师芯片项目 / 基础设施工程预算面向内部云工作负载的定制 AI 加速器芯片或工程 VP(可能)战略性自有 AI 芯片需要缩短排期
无晶圆厂先进制程芯片公司设计平台负责人或物理设计总监模块负责人、实现团队、验证负责人中央 EDA / R&D 预算CPU、GPU、网络或加速器 SoC 收敛CAD / 设计平台高管昂贵设计面临 PPA 压力,收敛循环反复拉长
自研定制 ASIC 的系统 / 电子公司SoC 项目负责人或产品工程负责人较小的内部芯片设计团队,加外部服务业务单元工程预算用于差异化设备或子系统的定制 ASIC产品或工程 GM需要把更多芯片差异化能力内化,同时不把路线图拖慢数年
设计服务 / IP 集成伙伴服务线负责人或方法论负责人实现工程师项目利润率 / 服务预算设计迁移、实现,以及重度复用流程实践或交付负责人需要压缩迭代时间,并提高客户项目之间的复用率
扩大使用范围的现有 EDA 点工具用户公司 CAD 或方法论负责人已在使用版图 / PPA 工具的现有模块团队企业软件预算从点状自动化扩展到更广泛的工作流标准化中央 EDA 治理团队需要证明自动化能从单个模块延伸为组织层面可重复的工作流收益

预算负责人标签部分来自现有工具的公开描述;准确审批路径仍是尽调缺口,不应把它说成既定事实。

[CM015, CM031, CM032, CM033, CM035, CM040]
FM003: 买方 / 细分市场地图

Ricursive 最可能早期细分市场中的买方、用户、付款方关系和准备度。

准备度和匹配度是基于公开工作流描述和买方痛点信号作出的顺序判断,不基于 Ricursive 披露的赢率或客户推荐。

[CM003, CM015, CM031, CM032]
FM004: 采用漏斗或价值链地图

由证明牵引的采用路径:从基准可信度到企业工作流标准化。

这个漏斗是机制模型,综合了在位 AI-EDA 工具的公开描述,以及独立质疑基准证明时暴露的信任顾虑。

[CM032, CM035, CM036, CM040]

2.4 增长驱动、采用约束与估值相关性

需求侧是真实的。超大规模云厂商已经规模化运行自研硅片项目:AWS 推广用于 AI 训练和推理的 Trainium,Google 称 TPU 支撑 Gemini 和更广泛的 AI 栈,Microsoft 称 Maia 200 改善其自有机群内的推理经济性。再叠加 Lightspeed 的观点——顶级硅片项目仍会消耗数年和数亿美元——增长驱动逻辑很强。Ricursive 不需要全世界每家半导体公司都购买其平台才有意义;它只需要在时间和人才最稀缺的定制硅片项目中拿到有意义份额。 约束侧同样重要。公开证明仍在布图规划和 PPA 优化上最强,而验证和全栈自动化等更宽主张尚未得到具名设计胜利或公开基准支持。New Scientist 对 AlphaChip 公开证明的怀疑很重要,因为关键任务设计软件买方对可复现性、保密性和切换成本异常敏感。出口管制又增加了一层摩擦,因为它会塑造哪些客户、晶圆厂和伙伴可以被干净服务。估值上,这意味着 Ricursive 应围绕证明里程碑和企业采用证据承销,而不是只靠宽口径 TAM 叙事。[CM010, CM011, CM012, CM013, CM014, CM016]

增长驱动因素与约束表
驱动因素 / 约束方向时点含义尽调要求
超大规模云厂商定制芯片竞赛正向现在至 2028 年以后买家仍急于缩短设计周期,也更愿意在战略项目上测试自动化梳理活跃的自有芯片路线图,以及哪些环节的排期压缩价值最高
现有 AI-EDA 厂商的验证点正向现在AI 辅助设计采购被正常化,Ricursive 在工程团队内部也更容易讲清楚用现有厂商案例对标 Ricursive 的试点主张
布局规划与 PPA 痛点正向持续存在设计周期长、手工收敛循环反复,构成高价值待解问题量化每个先进制程项目的人工、算力与排期成本
从布局扩展到验证若证实则正向2026-2028若 Ricursive 从点工具进入平台预算,SAM 会显著扩大要求提供公开或客户背书,证明验证能力在实践中跑得通
嵌入既有 EDA 栈的切换成本负向持续存在即便点性能更优,若集成与方法论风险太高,也未必能转化在试点中测试迁移工作量、工作流互操作性与回滚选项
窄任务之外的公开证明缺口负向现在缺少具名胜利、定价与验证基准,商业信任低于标题叙事要求提供基准包、客户背书与可重复性证明
出口管制与执法风险负向现在至 2026 年以后在先进制程项目中,客户组合、晶圆厂关系或伙伴工作流可能受限审查目标账户对 BIS 管制的暴露,以及任何晶圆厂或云伙伴限制
晶圆厂设备与 AI 需求热潮正向但间接2025-2026支撑定制芯片的战略价值,但不直接决定 Ricursive 的 TAM将硬件背景数字与软件市场规模主张分开

这张驱动因素表把采用力量和市场规模分母分开。庞大的硬件需求数字有助于解释紧迫感,但这些力量要转化为软件预算,Ricursive 仍需先证明工作流可信。

[CM010, CM012, CM013, CM014, CM019, CM020]

2.5 图表

Chapter 03

03竞争格局

3.1 直接商业替代品是既有 EDA 套件,而不是其他早期创业公司

AI 辅助芯片设计已经是商业品类,Ricursive 进入的不是空白市场。Synopsys 将 DSO.ai 定位为自主 RTL-to-GDSII 全流程优化;AWS 将其描述为强化学习软件,能在数周而非数月内搜索巨大的设计空间,同时改善功耗、性能和面积。Cadence 将 Cerebrus 定位为 AI 驱动的全流程优化器;到 2026 年初,其叙事已延伸到 ChipStack AI Super Agent,Forbes 称其为自动化芯片设计和验证的智能体工作流,并宣称生产率提升 10x。这两个既有厂商是最重要的直接替代品,因为许多潜在 Ricursive 买方已经授权 Synopsys 或 Cadence 工具,可以在不改变主要采购、签核或支持关系的情况下扩大 AI 使用。 Ricursive 仍有差异化叙事。公司官网、发布材料和伙伴文章把它描述为在打造全栈、自我改进的平台,而不是单点优化工具。如果买方想要跨放置、验证和架构探索的自动化,而不是既有流程里的更好调参引擎,这种雄心可能很重要。但今天的公开证据仍偏叙事:保留的公开客户引用中,没有显示 Ricursive 在生产环境击败 DSO.ai 或 Cerebrus。未来一到两年,买方的实际选择更可能是扩展既有工具还是试用 Ricursive,而不是 Ricursive 与另一家同等规模创业公司对决。[CP001, CP002, CP003, CP004, CP005, CP006]

竞品画像表
替代方案类别规模 / 融资代理指标目标客群产品范围差异化局限
Ricursive Intelligence直接初创公司已融资 $335M;估值 $4B(2026 年 1–2 月公开记录)先进芯片设计团队、前沿 AI 实验室、推进定制芯片的公司面向半导体设计的 AI 平台;声称具备全栈递归改进闭环创始人来自 AlphaChip,加上全栈野心无公开定价、客户名称、安全 / 合规披露或基准胜利
Synopsys DSO.ai(AI 设计优化)直接现有 EDA 厂商市值 $86.91B;TTM 收入 $8.00B已使用 Synopsys 流程的大型半导体团队自主 RTL-to-GDSII 设计空间优化装机基础、RL 优化、AWS/HPC 部署路径公开叙事以优化为中心,定价未披露
Cadence Cerebrus + ChipStack AI Super Agent(AI 设计代理)直接现有 EDA 厂商市值 $106.17B;TTM 收入 $5.52B已在 Cadence 上做数字实现与验证的团队AI 驱动的全流程优化,加智能体设计 / 验证工作流既有设计流程覆盖,以及 2026 年智能体路线图定价未披露;买家可能留在 Cadence 套餐内,而不是测试初创公司
AlphaChip / circuit_training(开源训练流程)相邻替代品——开源内部自建开源代码库;无需外部软件支出顶尖内部芯片与研究团队使用分布式深度 RL 做芯片布局规划免费代码与创始人谱系可信度只覆盖部分工作流,且需要专门人才与算力
Google TPU 组织相邻替代品——内部芯片Google 规模自有芯片,服务 >1B 用户 AI 场景拥有内部芯片团队的超大规模云厂商与平台定制加速器加内部工具证明最大买家可在内部解决硬件瓶颈不对外销售;相关性主要在于自建还是外购的替代选项
AWS Trainium / Annapurna相邻替代品——内部芯片超大规模云厂商自有芯片项目,针对规模化经济性优化云平台与超大型模型构建者专为 AI 训练与推理打造的芯片经济性优先的内部芯片战略仅内部使用;对非超大规模云厂商来说昂贵且组织要求高
Microsoft Maia 组织相邻替代品——内部芯片超大规模云厂商自有芯片,公开声称基准表现对标 Trainium 与 TPU具备推理规模的大型平台所有者Microsoft 异构 AI 基础设施中的内部推理加速器已发布的单位美元性能主张强化了内部自建理由不是外部工具,且仍绑定 Microsoft 自身技术栈
商用加速器(NVIDIA / AMD)现状替代品NVIDIA 市值 $4.969T / 收入 $215.93B;AMD $834.16B / $34.63B需要 AI 算力、但不愿承担定制芯片设计风险的企业购买成品加速器,而不是设计定制芯片最快采购路径与最强生态深度无法形成客户自有芯片差异化

公开规模代理指标使用 2026 年 6 月的市值页面与 TTM 收入页面。内部芯片组织是买家待办任务的替代方案,不是直接 EDA 供应商。商用芯片归为一组,因为买家的选择常常是购买加速器,而不是启动定制 ASIC 项目。

[CP001, CP002, CP003, CP004, CP005, CP006]
FP001: 竞争定位地图

在两条有证据支撑的轴线上,对 Ricursive 和关键替代方案作顺序定位:x = 分销 / 采购能力,y = 自动化广度 / 战略控制。Ricursive 野心分高,但已安装分销弱;在位厂商分销最强;内部硅组织战略控制最强。

分数是分析师顺序判断,锚定于保留公开证据中的安装基础、打包方式、工作流范围,以及自研还是外采的控制力。它们不是基准输出,也不是标准化 TAM 分数。

[CP005, CP007, CP021, CP022, CP023, CP025]

3.2 开源传承、内部硅片团队和商用芯片制造替代压力

Ricursive 还暴露在非直接软件供应商的替代品下。创始人背后的 AlphaChip 传承现在部分通过 Google Research 的 circuit_training 仓库开源,该仓库用分布式深度强化学习复现了 Nature 2021 年芯片布图规划方法。Sequoia 和 Ricursive 相关来源称 AlphaChip 将布图规划从数月压缩到数小时,但独立报道没有那么干净:TechCrunch 和 New Scientist 复述了三代 TPU 部署记录,并指出专家仍在争论公开证据能否证明其相较专家设计师或商业工具具备超人类表现。这个组合在竞争上重要:它验证创始人的技术履历,同时也说明成熟买方可以在内部研究或改造部分布图规划栈,而不是付费给新供应商。 更大的替代威胁是内部硅片。Google、AWS 和 Microsoft 都公开描述了自研 AI 加速器——TPU、Trainium 和 Maia——用于优化各自平台内的训练或推理经济性。Microsoft 的 Maia 200 页面更进一步,把自身与 Amazon Trainium 和 Google TPU 做基准对比。它们不是直接 EDA 竞争对手,但说明最先进的 AI 基础设施买方常会通过搭建内部芯片组织和自研工具链来应对硬件瓶颈。更朴素的替代方案,是直接从 NVIDIA 或 AMD 购买商用加速器,而不是启动定制 ASIC 项目。对许多企业来说,这种现货选择在运营上比采用新的 AI 芯片设计平台更容易。[CP013, CP014, CP015, CP016, CP017, CP018]

功能 / 能力矩阵
采购标准RicursiveSynopsys DSO.ai(AI 设计优化)Cadence Cerebrus / ChipStackAlphaChip / circuit_training(开源训练流程)超大规模云厂商内部芯片组织商用芯片(NVIDIA/AMD)
工作流广度声称是全栈半导体设计平台RTL-to-GDSII 优化全流程优化加验证智能体仅布局规划面向自有芯片的端到端内部栈无设计工作流;成品硬件
公开自主 / 智能体主张是——自我改进的递归闭环是——自主 AI 应用是——AI 超级智能体加生成式优化否——开源方法,不是打包智能体部分——自研内部工具,不对外销售
已安装企业采购基础尚无公开证明仅限各超大规模云厂商内部是——标准硬件采购
开源可得性
核心价值主张压缩更多设计周期,并闭合 AI 硬件循环改善 PPA 并缩短设计时间提高 PPA / 生产率,并自动化验证意图低成本复现实验室布局规划研究谱系超大规模云厂商获得最佳内部经济性 / 控制力获得 AI 算力容量的最快路径
公开披露定价是——免费 / 开源未对外定价硬件目录价 / 合同价因供应商而异
保留证据集中的公开客户证明未具名披露了合作伙伴部署路径,但此处未保留独立客户案例保留了产品主张与 Forbes 报道,但此处未保留具名基准胜利仅研究谱系超大规模云厂商内部使用公司规模暗示广泛市场采用
最适配买家想要外部 AI 自动化、但不自建超大规模云厂商级技术栈的团队现有 Synopsys 客户现有 Cadence 客户研究密集型顶尖设计团队超大型平台所有者相比设计芯片,更愿意购买算力的买家

标为“尚无公开证明”等的单元格反映证据限制,而非产品不存在。超大规模云厂商行描述的是替代行为,而不是外部软件打包。

[CP001, CP004, CP005, CP006, CP007, CP008]
FP002: 采用摩擦能力地图

定性矩阵,对比 Ricursive、直接在位厂商和关键替代方案在采购决策最看重能力上的表现。

「公开证明水平」指本章保留的公开证据,不代表整体市场真相。「部分到较广」表示在位厂商主张已超出单一点工具,但仍放在既有 EDA 工作流内表述。

[CP001, CP005, CP007, CP015, CP017, CP021]

3.3 切换成本和公开披露缺口目前有利于既有厂商与替代品

公开包装对比并不对称。Synopsys 和 Cadence 把 AI 功能呈现为既有企业流程的扩展,Synopsys 还特别把 DSO.ai 与 AWS ParallelCluster、AWS Batch 和 Slurm 式 HPC 编排配套。Cadence 强调可复用的优化模型和设计师控制台,让工程师留在现有流程中。这些事实意味着,已经押注既有厂商栈的买方部署摩擦更低。相比之下,Ricursive 的公开材料描述的是雄心、融资和团队质量,但没有披露定价、合同结构、安全证明、合规状态或具名客户胜利。这不代表公司没有这些东西;它意味着公开尽调尚不能把 Ricursive 视为已被企业验证。 替代品在采用摩擦上也表现不错。circuit_training 是开源的,但只有具备强化学习和物理设计能力的精英团队才可能把它运营化。超大规模云厂商内部建设很昂贵,却给买方完整控制权。来自 NVIDIA 和 AMD 的商用加速器根本不需要采用设计工具;它们靠硬件采购而非定制设计解决近期算力需求。这让 Ricursive 被挤在中间。它近期最好的切入点不是最低摩擦部署,而是证明它能比既有单点工具或自建替代方案提供更广的自动化和更快迭代。[CP005, CP006, CP007, CP020, CP021, CP025]

定价 / 打包对比
替代方案公开价格 / 单位合同模式买家获得什么切换 / 实施负担对 Ricursive 的含义
Ricursive Intelligence未披露未知;可能是企业软件加服务 / 算力,但缺少公开证据声称是全栈 AI 半导体设计平台中到高,因为买家必须加入新供应商,并信任新工作流主要公开缺口不是标价,而是基准与采购证明
Synopsys DSO.ai(AI 设计优化)未披露Synopsys 流程内按报价销售的企业软件既有 RTL-to-GDSII 栈内的自主优化对现有 Synopsys 客户较低即使 Ricursive 范围更广,现有厂商套餐也会降低采用摩擦
Cadence Cerebrus / ChipStack未披露Cadence 流程内按报价销售或打包的企业软件优化加新兴智能体设计 / 验证工作流对现有 Cadence 客户较低Ricursive 进入评估前,Cadence 就能先守住账户控制权
AlphaChip / circuit_training(开源训练流程)免费 / 开源代码自托管开源工作流可复用的布局规划方法,配分布式 RL技术负担高;软件支出低替代最精英的团队,而非普通企业买家
超大规模云厂商内部自建无外部价格;内部 capex 与工程支出内部组织加自研工具完全控制芯片路线图与经济性固定成本承诺极高只有最大买家能选这条路,但这些买家也是战略上重要的潜在客户
商用加速器(NVIDIA/AMD)硬件购买或容量合同;价格因产品和采购量而异标准硬件采购无需定制芯片设计即可立即获得 AI 算力工作流变化最低对不需要自有芯片的买家来说,这是最强现状替代品

保留的公开来源没有披露 Ricursive、Synopsys 或 Cadence 这些产品的标价。因此,对比重点放在打包、实施负担与买家含义,而不是假装已知合同经济性。

[CP005, CP006, CP007, CP020, CP025, CP026]

3.4 Ricursive 的护城河有可能成立,但公开证据中仍大多未证实

Ricursive 确实有可信资产。创始团队正在商业化一条真实的科学和产品传承:从 AlphaChip 延伸到 RL-CCD、Insta 和 C3PO 等后续工作;公司还称团队有开发 Gemini、Claude、Grok 和 TPU 的实操经验。这个组合让它在 AI 辅助芯片设计上具备异常强的创始人与市场匹配度。如果 Ricursive 能把这种履历转化为一种工作流,显著压缩那些规模不足以自建超大规模云厂商级内部系统的团队的设计收敛周期,它就可能在既有 EDA 套件和自建工具之间切出差异化位置。 当前公开证明负担仍很高。同一条开源 AlphaChip 传承提升了可信度,也限制了单靠宏观放置能形成多少护城河。与此同时,Synopsys 和 Cadence 明显在走向更广泛的自主和智能体自动化,压缩了 Ricursive 作为唯一有雄心全栈叙事的窗口期。最可能的商品化路径,是 AI 功能被打包进既有 EDA 平台和内部工具链,同时许多客户继续通过购买 NVIDIA 或 AMD 硬件完全避开定制硅片。除非 Ricursive 发布客户结果、基准证据或更清晰的企业包装,否则它的竞争案例在理论上有吸引力,但在分销、信任和证明上仍处劣势。[CP029, CP030, CP031, CP032, CP033, CP034]

护城河耐久性 / 竞争风险登记表
护城河主张优势来源威胁严重程度缓释 / 尽调要求
AlphaChip 创始人背景AI 辅助芯片设计中稀缺的技术谱系公开证明尚未显示 Ricursive 今天能打赢商业现有厂商要求提供相对 DSO.ai/Cerebrus 的客户基准数据与量产参考设计
全栈递归闭环野心范围可能比点状优化工具更广在 Ricursive 拿到分销之前,现有厂商已从优化延伸到智能体工作流要求提供当前工作流覆盖图、验证深度与路线图证明点
精英人才密度团队声称有来自 DeepMind、Anthropic、NVIDIA、Cadence、Apple、xAI、Gemini、Claude、Grok 与 TPU 的经验单靠人才无法解决企业采购或支持信任要求提供组织架构、客户支持计划与部署工程招聘计划
开源谱系可信度AlphaChip 与 circuit_training 验证了科学基础开源泄漏会削弱仅靠宏观布局形成的护城河中高区分今天哪些资产是自研的:数据、编排、模型反馈闭环与集成资产
初创公司敏捷性可围绕现代 AI 工作流设计产品,不背历史包袱与现有厂商的企业预期相比,缺少公开客户、定价或合规披露要求提供 SOC2 / 安全态势、采购准备度与具名设计胜利
现有厂商账户控制Synopsys 与 Cadence 已经坐在客户签核流程中买家在现有厂商栈内升级,而不是评估 Ricursive严重量化 Ricursive 能在哪里落地而无需推倒重来式替换,以及哪类买家角色掌握预算
内部自建替代品最大平台可用自研芯片 / 工具链回应最好的潜在客户可能永远不会购买外部软件中高GTM 聚焦非超大规模云厂商团队:他们仍需要定制芯片,却无法自建内部工具
商用芯片后备选项NVIDIA 与 AMD 可立即提供算力客户推迟或直接取消定制芯片项目瞄准差异化芯片经济性或供应独立性能证明设计投入合理的用例

严重性为定性判断,反映截至 2026-06-13 的发生概率乘以战略影响。该风险登记表同时纳入直接供应商威胁和自研替代,因为两者都会影响 Ricursive 能否拿到预算。

[CP013, CP017, CP021, CP027, CP029, CP030]
FP003: 护城河 / 准备度 KPI

截至 2026-06-13,概括 Ricursive 竞争姿态的紧凑指标。

[CP009, CP010, CP011, CP012, CP020, CP022]
Chapter 04

04财务情况

4.1 收入模式与变现架构

Ricursive 的公开材料对变现只支持一个窄口径财务结论:公司在打造设计芯片的 AI 工具,而不是向市场销售硅片的芯片制造商。TechCrunch、公司官网和发布材料都指向一个面向半导体设计的全栈软件平台,产品范围从放置延伸到验证和架构探索。这很重要,因为其可能的经济模型是卖入芯片设计工作流的企业软件,而不是晶圆代工收入、库存周转或硬件毛利率。 未公开的内容几乎同样重要。保留来源均未显示标价、用量费率、合同期限、收入确认政策,甚至没有具名设计伙伴。也没有公开自助漏斗或免费试用动作,无法支持产品驱动 SaaS 变现路径。因此,公开记录只支持潜在变现面——企业平台授权、试点项目,以及支持或集成工作——而不是已验证收入流。因此,本章把已披露融资之外的每一条收入线都视为未披露,除非直接来源另有说明。[CI001, CI002, CI003, CI004, CI005, CI006]

收入来源表
来源 / 触点机制单位当前价值 / 状态质量尽调问题
企业平台许可 / 订阅面向半导体工作流销售的 AI 芯片设计软件平台未披露合同 / 席位 / 项目口径未公开定价,也未描述合同条款索取定价材料、标准条款清单,以及按产品线拆分的已签约 ARR
试点或设计伙伴合作早期账户很可能采用技术评估和共同开发打法未披露试点结构未公开披露具名设计伙伴索取试点清单、转化率和平均试点周期
验证 / 工作流扩展平台范围延伸到验证和架构探索未披露能力已公开描述;变现方式未披露索取模块级变现地图和附加率假设
支持 / 集成服务围绕关键芯片设计流程落地,可能存在服务层未披露服务范围没有计费服务收入的公开证据索取服务 SOW 样例,以及服务相对软件的毛利拆分
硅片制造或芯片销售直接销售芯片或晶圆代工产出N/A公开来源称 Ricursive 设计芯片,而不是制造芯片确认不存在硬件库存或制造收入线

各行区分公开来源能够支持的内容,以及仍属假设的内容。Ricursive 的变现触点看起来类似企业软件,但没有公开来源披露实际定价、收入结构或转化数据。

[CI001, CI002, CI003, CI004, CI005, CI006]
定价 / 变现表
公开定价项价格 / 单位 / 合同标价与实际成交价折扣 / 未知项来源
标准订阅定价未披露官方网站或新闻稿材料中未找到公开价目表Ricursive 网站 / 发布新闻稿 / Series A 新闻稿
按用量计费的算力定价未披露未找到公开 GPU-hour、token 或工作负载价格Ricursive 网站 / 发布新闻稿 / Series A 新闻稿
合同期限未披露未公开披露年度、多年期或最低消费承诺Ricursive 网站 / 发布新闻稿 / Series A 新闻稿
试点 / 评估结构未披露未公开披露免费试点、付费试点或共同开发条款细节TechCrunch / Ricursive 网站
具名客户商业条款未披露未披露具名客户或交易金额TechCrunch / Ricursive 网站
公开披露的价值主张总拥有成本口径下性能接近 10x(公司主张,不是价格)公司主张的结果未披露实际成交价或按客户队列拆分的 ROITechCrunch

这张表刻意以 null / 未披露单元格为主,因为 Ricursive 没有发布商业价目表。公开经济信息只有结果导向叙事,而不是变现细节。

[CI004, CI005, CI013, CI016, CI017]
FI001: 收入模型桥

从芯片设计工作流痛点到 Ricursive 潜在收入线的可公开支撑变现路径。图中标出证据从已披露事实转为未披露商业细节的位置。

平台节点之后的边,来自企业软件销售模式推断,因为 Ricursive 没有公开客户合同或定价。

[CI001, CI002, CI004, CI006, CI012]

4.2 GTM 动作与销售效率代理

Ricursive 既不披露客户,也不披露商业指标,可用的公开 GTM 代理只能来自招聘和工作流背景。Ashby 招聘板显示七个开放岗位,全部在 Palo Alto 现场办公;保留的每个岗位都偏技术或安全:EDA 算法、LLM 基础设施、软件基础设施、设计验证、研究和创始安全。这种模式说明,公司可见支出仍投向产品和技术执行,而不是规模化外勤销售组织。它也说明商业模式不是自助式;关键任务芯片设计软件通常通过技术评估、工作流集成和共同开发进入账户,而不是购物车转化。 缺少公开客户引用,意味着 CAC、回本周期和周期长度无法从公开证据测量。不过,工作流背景仍重要。如果 Ricursive 卖入 AMD、Intel、NVIDIA 或超大规模云厂商级质量门槛的先进芯片项目,销售动作可能是高接触、技术中介型,即便最终毛利率轮廓看起来像软件。这形成了熟悉的私人公司模式:早期支出看起来研发偏重,而 GTM 效率在公司开始具名试点、转化和扩张队列之前仍无法验证。[CI007, CI008, CI009, CI014, CI015, CI016]

单位经济表
指标数值 / null置信度重要性尽调问题
收入 / ARR / 收入运行率收入规模是所有毛利率和现金跑道模型的起点索取月度收入桥、ARR,以及积压订单或管道转化数据
毛利率决定 Ricursive 更像软件公司,还是算力密集型研究基础设施索取云 / GPU、许可、支持和人员成本的 COGS 拆分
CAC / 回本周期判断企业分销是否资本效率高索取销售与营销支出、新客户数量,以及按客户细分拆分的回本周期
销售周期关键任务设计软件通常需要很长的技术评估周期索取试点周期中位数、上线时间和扩张节奏
公开可见招聘规模7 个开放职位;全部要求 Palo Alto 现场办公小规模技术招聘清单表明,公开可见支出仍集中在研发索取当前按职能拆分的员工数和 12 个月招聘计划
传统芯片设计周期基准2–3 年为客户愿意为周期压缩付费提供参照验证 Ricursive 在生产中实际缩短哪些工作流阶段
传统芯片设计成本基准数亿美元;劳动力是主要驱动因素解释为什么即便只是温和提升效率,也可能给买方带来经济意义索取客户 ROI 案例,展示节省的工时和设计收敛改善
公开 EDA 可比公司规模Cadence 2025 收入 $5.29B / 市值 $106.17B;Synopsys 2025 收入 $8.00B / 市值 $86.91B如果 Ricursive 成为 EDA 记录系统的一部分,这一行展示上行情景索取管理层对哪家公开可比公司最贴近长期模型的看法
公开工程软件可比公司规模Ansys TTM 收入 $2.58B / 市值 $32.90B;Autodesk TTM 收入 $7.20B / 市值 $41.89B设计中心型软件无需晶圆厂经济,也能做到数十亿美元收入和股权价值索取管理层看法:Ricursive 应该对标 EDA 席位、CAD 工作流,还是更广义的工程软件预算
公开半导体 IP 可比公司规模Arm TTM 收入 $4.67B / 市值 $406.73B半导体价值可以沉淀在设计 / IP 层,而不必拥有晶圆厂索取管理层看法:长期更接近许可模式,还是工作流订阅模式
公开晶圆代工可比公司规模TSMC 2025 收入 $121.91B / 市值 $2.198T澄清堆栈另一端规模更大、但资本开支更重的制造环节;Ricursive 并不像这一类确认不存在库存、晶圆代工产能或制造资本开支业务线

Ricursive 未披露私有指标的地方,null 单元格刻意保留。非 null 行是 EDA、工程软件、半导体 IP 和晶圆代工层的公开代理指标,不能替代公司自身单位经济。

[CI008, CI009, CI010, CI017, CI019, CI021]
FI002: 单位经济桥

从客户设计痛点到 Ricursive 可能内部支出结构的经济桥。Ricursive 特定利润率仍未披露,因此证据缺失处保持定性。

Ricursive 特定收入、CAC 和利润率数值被有意省略,因为公开记录不支持这些指标。

[CI009, CI010, CI011, CI017, CI018, CI026]

4.3 成本结构与代理经济性

最能站住脚的成本结构视角来自相邻证据,而不是 Ricursive 披露。Lightspeed 称,最先进的硅片项目可能耗时两到三年、花费数亿美元,劳动力吸收半导体研发支出的大部分。TechCrunch 和 Sequoia 补充说,AlphaChip 式方法能把布图规划从数月或一年多压缩到数小时。合起来看,这些来源意味着 Ricursive 试图变现一个有意义的客户成本中心:昂贵工程时间和漫长迭代周期。 公开类比公司也界定了上行空间和边界条件。Synopsys DSO.ai 和 Cadence Cerebrus 已经销售 AI 辅助设计优化,Forbes 称 AI 现在已用于约 20–40% 领先 SoC 设计,Cadence 则推广 10x 生产率提升。更广的可比公司栈让经济图景更清楚:Ansys 和 Autodesk 显示,以设计为中心的工程软件可达到 $2.58B 和 $7.20B 收入,对应 $32.90B 和 $41.89B 市值;Arm 显示,半导体 IP 层即便不拥有晶圆厂,也能支撑 $4.67B 收入和 $406.73B 市值。TSMC 的 $121.91B 收入和 $2.198T 市值标出了规模更大但资本更重的晶圆代工端。这个跨度支持 Ricursive 的软件 / IP 上行情景,而不是制造情景,即便其递归模型-硬件闭环仍意味着可观的内部算力、实验和专业劳动力支出。[CI010, CI011, CI012, CI013, CI019, CI020]

FI003: 财务估计区间

有来源支撑的区间,用于框定 Ricursive 的机会和资本姿态,同时不编造私有收入或利润率指标。

区间仅限于来源支持的边界和已披露融资事实。公开证据不足,因此不引入 Ricursive 收入、烧钱速度或现金跑道估计。

[CI010, CI021, CI022, CI028, CI029, CI030]

4.4 资本充足性与融资依赖

Ricursive 的资本位置是最强的公开财务事实。公司于 2025-12-02 以 $750M 估值完成 $35M 种子轮并公开亮相,随后在 2026-01-26 宣布以 $4B 投后估值完成 $300M Series A。官网和 TechCrunch 后来把已披露累计融资定为 $335M。按简单算术,公开估值在不到两个月内大约上升 5.3x。对于一家仍不披露客户、收入、员工数或董事会条款的公司,这种融资速度很异常。 公开记录没有展示这轮融资背后的现金账本。保留来源均未披露手头现金、月度烧钱速度、现金跑道、债务工具、算力容量承诺,或除“加速 AI 驱动半导体设计”这类宽泛语言之外的资金用途细节。可见团队足迹仍小,因此相对公开可观察内容,Ricursive 看起来资本充裕,但资金部署节奏不透明。这意味着不能只通过头部轮次规模判断资本充足性;下一个真正触发点更可能是可重复客户采用和产品执行证明,而不是又一轮创始人驱动融资。[CI028, CI029, CI030, CI031, CI032, CI033]

资本充足性表
项目数值 / 状态公开证据含义尽调问题
种子轮2025-12-02 完成 $35M 融资,估值 $750M发布新闻稿、Crunchbase、Converge Digest创始团队进入公开市场时,资本已经很充裕索取准确的投前 / 投后条款和期权池处理方式
Series A 轮2026-01-26 以 $4B 投后估值完成 $300M 融资PRNewswire, TechCrunch, SiliconANGLE, DCD如果资金大部分尚未使用,资本缓冲很厚索取交割文件和任何分期拨款机制
已披露总融资$335M官方网站和 TechCrunch相对公开可见团队规模,资产负债表应当较强索取当前现金余额和烧钱桥
手头现金未公开披露无法把标题融资额转化为现金跑道索取最新资产负债表和不受限制现金金额
月度烧钱未公开披露公开证据无法判断现金跑道和资本充足性索取月度 P&L、烧钱速度和前瞻经营计划
现金跑道月数未公开披露下一轮融资时点没有公开依据索取管理层在基准和下行情景下的现金跑道模型
债务 / 项目融资义务未发现公开债务或项目融资披露可能干净,但没有披露不等于不存在索取债务明细、产能承诺和表外义务
计划资金用途概括为加速 AI 驱动的半导体设计并扩充团队Series A 新闻稿和公司网站方向上有用,但颗粒度太粗,难以承销索取按劳动力、算力、工具和 GTM 拆分的募资用途预算
可能的下一轮触发条件商业牵引力证明,而不是拿到种子资源根据融资速度和持续不透明推断下一次估值台阶很可能需要客户验证索取与下一轮融资或盈亏平衡计划挂钩的里程碑

资本事实证据充分;现金、烧钱速度、现金跑道和义务则不是。这张表刻意保留 null,而不是用公开记录无法支持的假设倒推现金跑道。

[CI007, CI028, CI029, CI030, CI031, CI032]
FI004: 资本强度 / 现金流图

该矩阵列出可能驱动 Ricursive 现金消耗的成本桶,以及各项成本已有的公开证据。

公开记录止步之处,矩阵刻意保持定性。它只映射成本强度和现金流未知项,不虚构烧钱速度或现金跑道。

[CI009, CI026, CI027, CI033, CI034, CI035]

4.5 财务结论与尽调阻塞项

反向情景不是 Ricursive 缺资本,而是公开承销仍更多依赖创始人履历和融资速度,而非已披露商业牵引力。New Scientist 提到,独立专家认为 AlphaChip 所称超人类优势的公开证明仍不足;这很重要,因为 Ricursive 的财务故事取决于能否把技术传承转化为买方愿意付费的客户价值。与此同时,TSMC 的公开年报和 SEC 文件档案提供了有用披露基准:成熟半导体相邻业务通常披露的信息远多于 Ricursive 当前披露。 因此,从公开证据得出的可投资结论很窄。Ricursive 可能有资本继续建设,公开可比公司集合也显示,成功设计软件可以在没有晶圆代工式资本开支的情况下承载软件式企业价值。但收入质量、毛利率路径、现金跑道和融资依赖都仍被缺失的私人数据卡住。除非公司披露或分享客户证明、合同结构、月度财务和 Series A 后治理文件,否则正确结论不是业务弱,而是业务仍不透明。[CI033, CI034, CI037, CI038, CI040, CI041]

公开财务缺口表
缺失的私有指标 / 材料对承销的影响精确尽调路径
定价表和标准合同条款没有价格架构,就无法判断实际变现和折扣索取定价材料、标准 MSA、SOW 模板和样例发票
具名客户、设计赢单和转化队列无法检验收入质量、集中度或试点到生产的转化索取客户清单、逐阶段漏斗,以及至少两个客户访谈
收入 / ARR / 积压订单收入规模完全不透明索取月度收入桥、已签约 ARR、递延收入和预测
毛利率 / COGS 明细无法区分软件经济和算力密集型服务经济索取毛利桥,拆分云 / GPU、人员和第三方工具支出
烧钱速度、现金跑道和现金余额即便融资轮很大,也无法判断资本充足性索取最新资产负债表、现金瀑布和现金跑道模型
按职能拆分的员工数开放职位不能替代真实组织成本结构索取当前员工数、薪酬区间,以及按部门拆分的招聘计划
Series A 股权结构表、董事会和投资人权利治理和清算优先层级仍未知索取股权结构表、章程、董事会材料和投资人权利协议
募资用途预算标题融资规模无法说明公司为下一里程碑是资本过剩还是资本不足索取募资模型,按劳动力、算力、许可和 GTM 拆分计划支出

表中每一行都是真正的尽调阻碍,而不是装饰性披露偏好。Ricursive 是私营公司,因此保留 null 和未披露值,不用投机估计替代。

[CI004, CI005, CI017, CI033, CI034, CI038]

4.6 图表

Chapter 05

05产品与技术

5.1 产品定义与用户任务

Ricursive 的公开产品最好被理解为面向半导体团队的 AI 设计自动化层,而不是芯片供应商。公司官网和发布材料反复把交付物描述为一个系统:加速芯片设计,并在 AI 模型与承载它们的硅片之间闭合递归循环。TechCrunch 把描述收得更具体,称 Ricursive 在打造设计芯片的 AI 工具,而不是自己制造芯片;还报道称平台旨在覆盖从组件放置到设计验证,并能跨连续芯片项目学习。这让买方任务更具体:缩短周期、减少人工迭代负担,并为不想搭建超大规模云厂商级设计组织的团队改善定制硅片经济性。证据在问题框定上最强,在包装上最弱。保留的官方来源均未披露定价、自助访问、客户名称或合同结构,因此公开记录支持的是宽工作流投资逻辑,而不是成熟商业界面。[CE001, CE002, CE003, CE004, CE005, CE006]

产品模块 / 资产矩阵
模块 / 资产主要用户状态 / 成熟度差异化尽调缺口
递归式设计规划层芯片架构和物理设计负责人公司主张 / 概念化,但处于叙事核心框定 AI 与硬件共同演进,而不是单点优化未披露公开 API、UI 或设计输入工作流
布局和优化引擎物理设计工程师有技术谱系支撑,但 Ricursive 产品证据是间接的AlphaChip 和 C3PO 谱系支撑其在布局级任务上的自动化可信度没有 Ricursive 专属基准可对比人工团队或既有厂商
时序分析 / 评估层时序 / 签核工程师通过 INSTA 获得谱系支撑,但尚未展示为 Ricursive SKU可微 STA 谱系表明,优化循环里可能有更快的评估器没有证据证明这一确切能力今天已在 Ricursive 出货
设计验证工作流验证工程师TechCrunch 公开提及,但披露不足叙事从布图规划延伸到更靠后的流程阶段未公开描述检查项、覆盖率或签核边界
跨芯片模型学习记忆平台 / 研究团队公开描述偏未来导向跨芯片学习叙事是相对单点工具最清晰的护城河主张尚无客户证据显示跨项目迁移学习成立
迭代所需算力基础设施研究 / 基础设施团队已融资并在扩张Series A 明确把资本与更快全栈迭代绑定未公开云厂商、集群规模或成本模型细节
开发者信号研究触点潜在技术评估者今天可见开源谱系和公开研究材料提升技术可读性大多数公开材料仍是研究级,而不是企业级封装
商业部署触点企业买方公开信息看不清可能成为小团队免自建设计团队做芯片的楔子定价、客户证据、支持 SLA 或安全资料包均未公开

各行把有技术谱系支撑的技术构件,与公开证据仍偏薄的封装、企业信任和已出货部署形态区分开。

[CE001, CE002, CE003, CE004, CE006, CE017]
工作流 / 用例表
用户任务当前工作流Ricursive 解决方案可衡量收益局限
宏单元布局和布图规划资深物理设计工程师要迭代数周或数月AlphaChip 式 RL 自动化布局搜索从数月压缩到数小时的布图规划,是公开基准中支撑最强的一项基准来自技术谱系材料,不是 Ricursive 客户案例
时序敏感优化团队反复重跑签核和局部时序修复INSTA/RL-CCD 谱系暗示优化循环中有更快的时序感知评估公开谱系指向亚秒级时序传播和差异化时序梯度没有公开证据显示 Ricursive 将其暴露为产品工作流
跨项目学习每个新芯片项目通常都从新的启发式规则开始Ricursive 称,每设计一颗芯片都应改进下一个设计器跨项目复用率可能更高,迭代也可能更快未发布公开部署或迁移学习结果
设计验证交接验证通常位于布局变更下游TechCrunch 称 Ricursive 也计划覆盖验证可能减少优化与验证之间的返工验证覆盖范围、工具链或验收标准没有公开细节
小团队获取定制硅能力非超大规模云厂商往往无法组建庞大芯片设计团队投资人材料把 Ricursive 定位为让小团队不用自建设计团队也能做定制硅可能把买方池从拥有大型内部团队的巨头之外继续拓宽没有公开案例研究显示小团队借助 Ricursive 完成流片
接入企业既有流程现有 EDA 买方已经使用 Synopsys 或 Cadence 技术栈Ricursive 需要接入这些流程,而不是一夜之间替代如果集成跑通,自动化范围可能比单点工具更广公开集成边界、签核路径和回滚计划仍未披露

收益表述来自最强的公开技术谱系证据和既有厂商对比背景;Ricursive 专属生产结果仍未在公开层面得到证明。

[CE004, CE011, CE017, CE019, CE023, CE027]
FE002: 客户工作流 / 运营流

从芯片项目痛点到假设性 Ricursive 部署,按证据边界梳理工作流,并标出公开记录从直接产品证据转为推断的位置。

节点 w2、w5 和 w6 反映公开来源暗示的实际交接点;Ricursive 尚未发布详细客户实施图。

[CE003, CE004, CE012, CE017, CE023, CE041]

5.2 架构与技术传承

Ricursive 技术故事中最可信的是传承。AlphaChip 的 Nature 论文和公开 circuit_training 仓库展示了真正用于布图规划的强化学习方法,而不是通用 AI 包装;Sequoia 和 Lightspeed 称,这条传承把布图规划从数月压缩到数小时,并用于四代 TPU。Ricursive 当前产品主张就建立在这层基础之上。公开来源称平台应能跨芯片学习,创始人具名传承现在还延伸到用于时钟与数据优化的 RL-CCD、用于可微时序分析的 INSTA,以及用于商业质量放置目标的 C3PO。这个推进很重要,因为它暗示了一条通往更广优化栈的路径:搜索、奖励建模、时序感知评估和放置质量目标。它也划出了边界。保留证据在研究产物上仍比 Ricursive 特定实施细节更丰富,因此外部尽调可见的架构是一种分层推断——优化引擎位于快速评估器之上,再叠在算力和既有流程依赖之上——而不是有文档记录的企业蓝图。[CE007, CE008, CE009, CE010, CE011, CE023]

技术 / 运营架构表
层级 / 流程 / 组件角色依赖风险
设计意图摄取将工作负载或架构目标转译为优化目标客户设计数据、约束和封闭 EDA 输入没有公开证据说明文件格式、API,或如何处理封闭 PDK 数据
优化策略层在大设计空间里搜索更优布局 / 收敛选择来自 AlphaChip 谱系的强化学习或学习型搜索技术从技术血缘迁移到 Ricursive 产品有合理性,但尚未直接跑基准验证
快速评估器与奖励模型快速给候选布局和时序结果打分时序分析引擎、布局指标、可布线性与线长估算器公开证明存在于血缘成果中,不是 Ricursive 的企业文档
验证与签核边界验证改动能否在优化循环之外站得住外部验证工具与既有签核系统Ricursive 尚未公开说明平台在哪里收口、签核从哪里开始
计算与编排底座快速且经济地跑大量设计实验云或内部集群,加上调度 / 编排集群拓扑、工作负载路由、故障处理没有公开细节
既有 EDA 互操作接入以 Synopsys / Cadence 为中心的客户流程客户许可证、脚本、PDK 与流程所有权除非 Ricursive 能顺畅补强既有流程,部署摩擦可能仍然很高
治理与地域合规层筛查客户项目和技术访问出口管制政策与客户尽调半导体和 AI 管制会限制产品可销售的地点与方式

这张架构表只映射留存来源中可见或可推断的层。缺失的集成细节保留为风险,不用猜测填平。

[CE003, CE014, CE017, CE023, CE025, CE031]
FE001: 产品架构图

分层看 Ricursive 的公开叙事:顶层是递归产品逻辑,中层是有技术谱系支撑的优化引擎,底层是算力和既有流程依赖。

[CE002, CE003, CE017, CE023, CE025, CE031]

5.3 差异化与部署约束

Ricursive 的公开差异化说起来比验证起来容易。面对 Synopsys DSO.ai 和 Cadence Cerebrus,公司主张的重点不是更好的单一优化引擎,而是一个更广的递归平台,能跨项目学习,并最终连接设计、评估和硬件共同演进。这在战略上有吸引力,尤其适合缺少巨型内部硅片组织的买方。但部署现实仍绕不开既有厂商和基础设施。Synopsys 和 Cadence 已经在根深蒂固的流程内销售 AI,DSO.ai 明确绑定 AWS 编排,Cadence 也越来越向智能体验证延伸。与此同时,TPU、Trainium 和 Maia 等超大规模云厂商栈显示,一些先进潜在客户会在内部解决硬件瓶颈,而不是新增一家设计平台供应商。再叠加先进半导体出口管制治理,实际图景很清楚:Ricursive 可能必须嵌入现有设计环境,证明数据和签核信任,并处理政策约束,然后递归平台故事才会在运营上起决定作用。[CE013, CE014, CE015, CE016, CE031, CE032]

路线图 / 发布 / 开发阶段表
日期 / 阶段功能或里程碑状态含义来源
2021 / 研究里程碑Nature AlphaChip 论文已发表公司成立前,先建立了基于 RL 的布图规划血缘Nature / circuit_training(研究与代码)
2023 / 研究里程碑RL-CCD 获 DAC 最佳论文认可已公开描述创始人相邻血缘从布局扩到时钟与数据优化Synopsys RL-CCD 博客
2025 / 研究里程碑INSTA 获 DAC 最佳论文认可已公开佐证增加快速时序分析与可微分评估血缘INSTA GitHub / NVIDIA 发表页面
2025-12 / 公司发布Ricursive 带着种子轮融资和全栈 AI 芯片设计雄心发布已公开宣布在公开客户证明出现前,公司先以宽叙事进入市场发布 PR / 行业媒体
2026-01 / Series ARicursive 融资,用于扩展计算基础设施,并在全栈上更快迭代已公开宣布尤其在基础设施上,建设阶段仍在进行Series A PR / TechCrunch
2026 / 当前公开成熟度未找到公开客户背书、更新日志或信任资料包仍披露不足产品成熟度看起来技术雄心很高,但商业上不透明官方网站 / TechCrunch / Ashby / GitHub 渠道
2026 / 打包信号INSTA 和 circuit_training 开发者渠道显示代码与 issue,但没有打包发布已观察到研究级成果存在,但打包纪律仍显薄弱GitHub releases / issues 页面

这张路线图把公司里程碑和技术血缘里程碑放在一起,因为公开记录对技术来源的支撑强于对 Ricursive 自身交付节奏的支撑。

[CE007, CE009, CE024, CE025, CE026, CE040]
FE003: 关键依赖图

依赖图显示,Ricursive 大概率必须与既有 EDA、云算力和政策约束共存,而不是作为独立的奇迹盒子运转。

该依赖图把超大规模云厂商栈和出口管制视为实际上市约束,而非直接软件竞争对手。

[CE014, CE031, CE032, CE033, CE034, CE035]

5.4 信任、成熟度与运营就绪度

公开成熟度信号好坏参半。积极一面,Ricursive 不是纯空气项目:它有真实科学传承、可见开发者信号界面,以及强调 EDA 算法、LLM 基础设施、设计验证、软件基础设施、研究和安全的招聘足迹。这些都是严肃建设型组织的材料。薄弱一面是企业证明深度。保留公开记录没有浮现信任中心、认证、公开状态历史、发布说明、具名客户或签核边界文档。围绕 circuit_training 和 INSTA 的 GitHub 界面强化了这种分裂:有意义的公开代码和 issue 跟踪存在,但包装仍像研究级,公开仓库没有发布纪律。即便最新 C3PO 里程碑的佐证也比 AlphaChip 的旧记录更薄,因为保留的 ASP-DAC 公开档案尚未显示 2026 年条目。结果是一个技术上看起来可信、商业上记录不足的产品故事。尽调的下一步不是继续读叙事,而是索要客户引用、安全材料、集成图,以及 Ricursive 能经受生产流片流程接触的证据。[CE020, CE021, CE022, CE028, CE029, CE030]

信任 / 质量 / 合规表
控制项 / 证明点状态范围缺口
公开安全中心或信任门户留存公开材料中未找到外部买方尽调界面没有公开的证书清单、渗透测试摘要或架构说明
公开状态页 / 正常运行历史留存公开材料中未找到运营可靠性证明未公开故障历史、服务健康信息流或 SLA 界面
版本化发布 / 更新日志流未在 Ricursive 产品公开材料中找到发布纪律与已交付功能证明没有带日期的发布说明区分已交付能力和路线图
开源血缘代码circuit_training 和 INSTA 存在研究可信度与技术可读性研究仓库不能替代 Ricursive 产品控制
出口管制框架相关性BIS、CSIS 与法律分析中存在客户筛查与地域部署治理Ricursive 专属合规政策未公开
独立客户证明留存公开来源中未找到运营质量与买方信任未公开参考架构或客户运行结果

最强的公开信任信号来自研究开放度和通用监管语境,不是 Ricursive 专属安全或运营材料。

[CE019, CE036, CE038, CE040, CE041, CE048]
FE004: 产品成熟度 / 能力图

能力成熟度矩阵区分两件事:公开证据在技术谱系上较强,但在企业级封装和部署证明上较薄。

单元格取值是基于已保留证据质量的定性判断,不是内部公司指标或基准分数。

[CE008, CE017, CE023, CE027, CE030, CE040]

5.5 图表

Chapter 06

06客户情况

6.1 目标客户原型、买方-用户-付款方图谱与工作流位置

虽然公开记录不支持公开客户名单,但它支持相当具体的客户形状。Ricursive 卖的不是成品芯片,而是把芯片设计加速投资逻辑卖给那些已经背负昂贵硅片路线图、大额算力预算和痛苦 PPA 取舍的组织。这首先指向前沿 AI 实验室和超大规模云厂商,其次是大型无晶圆厂半导体供应商,再其次是因为推理规模或硬件差异化具备经济意义、因而能证明内部 ASIC 项目合理性的系统公司。可见类比都在这个世界里:TSMC 的庞大晶圆代工客户基础、AWS 和 Google 的定制硅片项目,以及优化先进制程 SoC 的 Cadence 和 Synopsys 客户。 在一个账户内,买方、用户和付款方不太可能是同一个人。买方可能是关心流片时间和总系统经济性的算力、平台或硅片项目负责人。用户更可能是活在 EDA 工作流里的物理设计、验证或架构团队。付款方则是为芯片路线图出资的更广企业预算负责人。这个分裂很重要,因为它意味着漫长、技术中介型销售动作,而不是轻量产品驱动采用。Ricursive 自己的招聘板强化了这种解读:公开招聘仍集中在 EDA 算法、基础设施、验证、研究和安全,而不是外勤销售或规模化客户成功。 Sequoia 的“designless”框架也有信息量。这个主张不只是让现有芯片团队工作更快;它还意味着更多公司可能成为芯片买方或芯片项目赞助方,而不必建立庞大的内部设计组织。如果这一投资逻辑成立,Ricursive 的 TAM 可能从传统无晶圆厂供应商延伸到想要定制硅片、但不想从零复制完整 Broadcom、Google 或 NVIDIA 式芯片组织的 AI 实验室和系统公司。但这仍是目标客户假设,不是 Ricursive 已证明的业务账本。[CU002, CU003, CU004, CU005, CU006, CU007]

客户分层表
细分买方主要用户付款方用例战略价值缺口
前沿 AI 实验室 / 超大规模云厂商计算、基础设施或硅项目负责人物理设计、验证与架构团队中央基础设施或 AI 平台预算加速定制 AI 加速器设计与协同优化没有具名 Ricursive 账户或转化证明
大型 fabless 半导体公司工程 VP 或 SoC 项目负责人模块工程师与实现团队芯片项目 P&L缩短先进节点芯片的 PPA 迭代时间需要证明 Ricursive 在生产中胜过既有 EDA 自动化
拥有内部定制硅的系统公司平台或硬件 GM内部 ASIC / 硅团队公司产品预算不以同样速度扩设计人头,也能做出差异化芯片中高公开 Ricursive 背书没有显示系统公司部署
商业设计服务 / 协同设计机构业务负责人或技术支持人EDA 与验证专家项目或客户出资的服务预算在多个客户 tapeout 中复用 AI 工具未披露公开的 Ricursive 设计服务合作
购买云端定制硅的 AI 原生模型公司模型或基础设施负责人ML 系统与线上服务工程师模型训练 / 推理预算用设计自动化缩短与模型经济性绑定的定制硅周期中高需求在 Ricursive 相邻区域可见,但 Ricursive 胜单未公开

分层反映公开工作流证据最能支撑的买方原型,不代表 Ricursive 披露过客户名单或收入结构。

[CU002, CU004, CU005, CU006, CU007, CU010]
FU001: 买方—用户—付款方与工作流图

Ricursive 可能卖进复杂的企业硅项目,其中经济买方、用户和付款方并不相同。

[CU005, CU006, CU010, CU032]

6.2 公开证明栈:相邻可信度真实,但 Ricursive 特定客户证明仍薄

核心客户事实是负面的,但很重要:Ricursive 的公开界面没有具名生产客户。TechCrunch 更明确,称创始人不愿透露早期客户名称。同一篇访谈确实报道了来自“每个大型芯片制造商”的强劲主动兴趣,并称 Ricursive 可以选择首批开发伙伴;这比零信号更好,但仍明显弱于具名账户、买方引语、流片案例研究或结果指标。发布稿中的“早期企业”措辞也属于同一类:它显示商业化意图,而不是客户证明。 更强的是相邻传承。DeepMind 称 AlphaChip 已用于多代 TPU,MediaTek 也将其扩展到先进芯片。Sequoia 播客补充说,创始人数年来把 TPU 团队视为内部客户,并围绕这些工程师真正关心的指标调优方法。这有意义,因为它证明她们以前解决过真实设计用户问题。但这仍是相邻证明,不是 Ricursive 收入证明。正确解读是,Ricursive 起点具备异常强的创始人与市场匹配度,也有异常弱的公开牵引力披露。 市场侧背景有助于解释投资人为什么愿意忍受这个缺口。Anthropic、AWS、Google、Microsoft 和其他平台建设者已经证明,当成本、吞吐量和控制权足够重要时,大买方会押注定制硅片路径。从这个意义上说,Ricursive 指向的是真实痛点。缺失的一步,是证明客户会把生产设计流程中有意义的一部分专门交给 Ricursive 信任。[CU001, CU012, CU013, CU014, CU015, CU016]

客户增长 / 采用轨迹表
代理指标公开数值 / 状态日期置信度含义缺失分母
具名 Ricursive 生产客户公开未具名2026-06-13公开牵引力证明仍薄底层客户数未知
未具名早期客户创始人不愿具名2026-02-16中高暗示已有账户活动或评估未披露阶段、客户标识或用例
第一批开发伙伴创始人称可以从中选择2026-02-16释放出主要芯片厂商主动接洽的信号没有合同数量或范围
相邻已部署血缘AlphaChip 用于多代 Google TPU,并由 MediaTek 扩展2024-09-26创始人在相邻工作流中规模化解决过问题不是 Ricursive 客户指标
目标市场定制硅需求Anthropic / AWS / Google TPU 承诺显示数十亿美元级平台采用2026经济性清楚时,大买方会投入不是 Ricursive 专属胜单证据

这些是公开采用代理,不是直接的 Ricursive 客户指标;没有披露分母或 Ricursive 部署数量时,表中保留该缺口。

[CU001, CU012, CU016, CU017, CU018, CU028]
具名客户证明表
参考对象与 Ricursive 的关系公开记录内容生产 vs 试点关键限制
未具名早期客户直接 Ricursive 信号TechCrunch 称创始人不会透露早期客户名称Unknown未披露客户标识、合同、用例或结果
未具名开发伙伴直接 Ricursive 信号TechCrunch 称大型芯片制造商已主动接洽,Ricursive 可以选择首批开发伙伴可能处于生产前 / 评估没有伙伴名称、范围或买方引述
Google TPU 团队 / Google Cloud TPU 血缘相邻创始人证明AlphaChip 曾用于多代 Google TPU,TPU 容量通过 Google Cloud 触达外部用户生产级相邻证明证明属于创始人此前工作,不属于 Ricursive 合同
MediaTek相邻外部采用方DeepMind 称 MediaTek 扩展 AlphaChip,用于先进芯片生产级相邻证明不是当前 Ricursive 收入账户证据

这张枚举表有意混合直接 Ricursive 信号与相邻证明,因为公开的 Ricursive 具名客户证明缺失;区别逐行保留。

[CU001, CU012, CU014, CU015, CU016, CU017]
FU002: 公开证明阶梯

可见证据从相邻的创始人证明延伸到未具名的 Ricursive 兴趣;具名 Ricursive 生产客户仍是明显缺口。

[CU012, CU015, CU016, CU017, CU038]

6.3 早期伙伴模糊性、渠道与采用约束

即使 Ricursive 拿下一个技术上很亮眼的试点,真正采用仍取决于一个公司无法完全掌控的生态。Cadence 和 Synopsys 的证据已经说明客户希望这些工具落在哪里:嵌在完整的数字设计流程里,并与验证、时序、物理实现紧密互动。AWS 的 DSO.ai 案例又补上一层落地条件:基础设施规模和可自动扩缩的 HPC 集群在实践中很重要。TSMC 的专用晶圆代工材料也从制造端指向同一个结论:严肃的硅客户买的不只是单一优化引擎,还包括支持、客户管理、工程服务和生态兼容性。 客户侧约束在 Ricursive 之外也看得见。Omdia 的 foundry-wall 分析称,先进封装和 HBM 至少到 2027 年中仍会是瓶颈。Morrison Foerster 的出口管制说明提醒读者,合规风险如今触及更广泛的 AI 芯片生态,而不只是晶圆厂和出口商。Data Center Frontier 对 Anthropic 的画像显示,成熟实验室会主动在 Trainium、TPU 和 GPU 之间分散布局,以保住供应和定价筹码。上述行为指向 Ricursive 面前一个细微但重要的客户要求:买家可能想要可移植性和互操作性,而不是把自己锁进某一家云、某一条晶圆代工关系或某一个验证栈的工作流。 因此,TechCrunch 所说的“首批开发伙伴”没有第一眼看上去那么关键。开发伙伴有用,但回答不了谁承担部署风险、谁签合同、谁支持流片,也回答不了一个设计从有希望的试点走向商业化硅片时,晶圆代工或出口延迟由谁吸收。渠道质量和生态匹配因此是核心尽调议题,不是脚注。[CU021, CU022, CU023, CU024, CU025, CU026]

扩张与集中度风险表
扩张驱动集中度或依赖风险影响尽调路径
旗舰账户拿下参考客户单一标杆客户可能主导叙事和议价能力索取头部账户敞口,以及主账户暂停时的情景分析
在更多芯片项目中先落地再扩张尚无公开证据表明一个试点会扩成多个生产项目中高审查每个账户的项目数和试点后扩张历史
通过云、代工厂或 EDA 生态获取伙伴引流伙伴杠杆会塑造定价、支持和实施控制审查具名互操作或联合销售协议
更快的 tapeout 或验证结果代工厂、封装和 HBM 瓶颈仍会推迟终端客户价值兑现区分哪些约束 Ricursive 能直接解决,哪些只能间接影响
全球客户触达出口管制和客户地域可能缩窄合法或实际可购买产品的人群获取客户地域、出口管制矩阵与受限用途政策

这些是围绕当前公开证据集的风险视角,不是按概率加权的收入预测。

[CU023, CU024, CU025, CU026, CU031, CU032]
FU003: 客户证明矩阵

相邻市场需求很强,但 Ricursive 专属证明和持久性证据仍然稀疏。

[CU011, CU018, CU021, CU023, CU026, CU034]
FU004: 试点到生产的尽调路径

即便 Ricursive 试点很有说服力,仍需跨过集成、流片、制造和扩张关卡,才能证明客户持久性。

[CU023, CU032, CU033, CU039, CU041, CU042]

6.4 耐久性、集中度,以及仍需补足的尽调

耐久性是公开证据最弱的一环。保留来源没有披露客户数量、试点到生产的转化率、合同期限、NRR、GRR、续约节奏,甚至没有清楚区分评估账户和生产账户。不能把这种缺失解读为失败信号;许多很年轻的基础设施公司都会把这些数字留在私下。但这也意味着,本章无法负责任地从创始人履历或融资速度推断留存质量、扩张效率或已安装客户基础的健康度。 公开记录同样无法量化集中度风险,而这种不可量化本身就是风险信号。一家公司可以拥有广泛的主动咨询兴趣,却仍在商业上依赖一两个标杆设计伙伴来完成验证、路线图反馈和未来订单。如果 Ricursive 第一个可见参考客户最终是一家前沿 AI 实验室或顶级芯片厂商,这个胜利会有战略价值——但也可能给客户带来谈判筹码,并扭曲公司的收入结构。在管理层披露更多信息之前,诚实的做法是保留这个缺口,而不是用尚未公开的客户 logo、NPS 或留存主张去填补。 客户尽调因此需要直接追问隐藏变量。最有决策价值的要求包括:具名参考客户包、带转化状态的试点漏斗、经遮盖的合同结构、在既有 EDA 栈中的工作流位置、流片或验证结果证据,以及已签客户和近期管线的集中度数据。Ricursive 很可能在 NDA 背后已经拥有优秀的早期客户。当前公开记录只是尚未证明这一点。[CU027, CU028, CU029, CU030, CU031, CU038]

留存 / 重复使用 / 满意度表
指标数值 / 状态细分置信度尽调问题
净收入留存率(NRR)空值 — 未公开披露全部 Ricursive 客户索取按队列拆分的账户级扩张与收缩
总留存 / 流失空值 — 未公开披露全部 Ricursive 客户索取试点和生产账户的续约与流失历史
合同期限 / 续约节奏空值 — 未公开披露全部 Ricursive 客户审查样本 MSA、试点协议与续约条款
试点到生产转化空值 — 未公开披露全部 Ricursive 客户获取带签署日期和转化率的销售漏斗阶段
工作流粘性代理集成的 EDA / 代工厂 / 云工作流意味着切换摩擦可能很高,但 Ricursive 尚未证明这一点可能是企业设计账户用客户背书和重复 tapeout 使用证据验证粘性

空值表示公开记录未披露该指标;最后一行是推断代理,不应误认为 Ricursive 留存证明。

[CU028, CU029, CU032, CU039]

6.5 展示材料

Chapter 07

07风险

7.1 风险概览:承销问题在于证明转化,而不只是技术雄心

Ricursive 的首要风险来自一条裂缝:技术出身极为亮眼,但商业化公开记录仍很薄。公司、投资人和独立报道都同意,芯片设计慢、贵且战略意义重大,这解释了 Ricursive 为什么能如此迅速融资 $335 million。但同一组证据也显示,公司进入的是一个现有巨头已经交付 AI 辅助设计产品的市场,先进节点验证仍然顽固地难,出口管制负担如今也延伸到远程访问、晶圆代工分配和客户筛查。公开证明主要来自创始人、投资人和继承自 AlphaChip 的可信度,而不是具名客户、披露收入或独立基准胜利。这让风险彼此联动:技术证明缺口会拖慢采用,采用缺口会放大估值风险,出口和晶圆代工约束会推迟部署,一个小型专业团队还必须同时吸收所有压力。因此,本章的基准情景不是“科研项目失败”,而是半导体创业公司更常见的失败模式:令人印象深刻的技术履历,未能足够快地转化为可重复的商业证明。[CR001, CR002, CR003, CR004, CR006, CR007]

缓释和终止标准表
风险可监控触发项阈值或事件行动含义
技术证明缺口独立基准复现在下一轮重大尽调周期内,未能拿出相对现有厂商或内部基线的第三方基准胜利不承销持久技术差异化;要求分阶段融资或放弃。
商业证明缺口具名客户证据到下一次融资步骤时,仍没有付费设计客户、生产部署或设计胜利引用将估值视为创始人溢价投机,而不是有证据支撑的平台价值。
出口管制准备度合规审计结果针对敏感地域,没有书面的出口管制负责人、KYC 工作流和外部律师审查在控制措施建立前,阻止国际商业化扩张。
供应链依赖代工和封装路径早期客户项目没有可信的 MPW、代工、封装或云算力路径下调客户转化时间表和与流片挂钩的收入机会。
团队集中度关键招聘完成验证和安全领导仍贴近创始人,缺少职能冗余提高关键人折价,并要求留任和招聘里程碑。
估值风险证明到价格的转化在客户、基准或合规里程碑实质改善之前,公司又募集新资本假设后续融资面临下轮或平轮压力,并重设入场价格预期。

这些触发项有意设计为可监控指标,让尽调把风险讨论转化为明确的推进 / 否决阈值。

[CR023, CR028, CR031, CR038, CR042, CR043]
FR001: 风险热力图

序数矩阵按可能性、影响、缓释成熟度和剩余严重性,展示 Ricursive 最重要的风险域。

[CR010, CR018, CR028, CR031, CR042, CR043]

7.2 技术执行风险与验证负担和现有巨头反应无法切开

核心技术风险不在于强化学习原则上能不能帮助芯片设计,而在于 Ricursive 能否比大型现有厂商更快,在当前客户问题上交付商业上更优、更可信的工作流。DeepMind 以及与 Ricursive 相关的材料提供了真实验证:AlphaChip 风格方法曾在 Google 的 TPU 项目中发挥作用,并影响了更广泛领域。这是实质性缓释因素。问题在于,最有力的独立批评在公开层面仍未解决;专家告诉 New Scientist,Google 尚未在可复现、公开、最先进的基准上证明优势,强化学习方法还可能落后于商业工具,同时消耗多得多的算力。与此同时,Cadence、Synopsys 和 Siemens 已经从点状工具推进到横跨 RTL、验证、物理实现、签核和先进节点使能的智能体编排。它们自己的产品发布仍承认同一件事:人工监督、签核纪律和有根基的 EDA 工作流仍不可少。因此 Ricursive 背着双重负担——既要证明技术优势,也要证明这套工作流安全、可验证,并且便宜到足以替换现有栈。[CR008, CR009, CR010, CR011, CR012, CR013]

运营 / 质量 / 安全风险登记表
失效模式重要性发生可能性影响现有缓释剩余风险未解决缺口
公开基准证明尚未坐实 Ricursive 的技术领先独立批评者仍认为,AlphaChip 式方法还没有拿出可复现证据,证明其能胜过现代商业基线。创始人确有 AlphaChip 背景和 Google 生产经验。在当前设计上完成基准测试之前,商业买家可能仍会把这套工作流视为尚未验证。没有公开的第三方基准,能在客户相关工作负载上对比 Cadence、Synopsys 或 Siemens。
即使进入智能体流程,验证和签核仍是瓶颈现有厂商的新产品仍围绕人和工具的编排展开,而不是彻底移除验证纪律。该品类如今有更强的自动化工具和更多算力。如果年轻技术栈增加签核不确定性,客户可能抵触替换。没有关于 Ricursive 验证吞吐、漏检或收敛率的公开数据。
算力强度可能侵蚀经济优势批评者认为,RL 方法消耗的算力可能远高于传统商业工具。中高中高算法改进和更好的硬件可能抵消部分负担。如果设计工作流技术上胜出、经济上输掉,就无法取代现有厂商。没有 Ricursive 每个设计或每次迭代成本的公开证据。
敏感设计流程会抬高安全和数据治理负担处理客户 IP、远程用户和智能体工具编排,会很早就拉高安全预期。公司公开招聘创始安全岗位,说明已意识到需求。在建设期,安全成熟度可能跟不上商业化野心。公司网站没有公开信任中心、认证或安全架构披露。
先进节点复杂度让执行门槛保持很高竞争对手和 TSMC 相关工具已经支持先进节点验证、DRC、热分析和多芯片分析。中高市场已经验证 AI 能提供帮助,创始人也深懂该领域。Ricursive 要赢下严肃项目,必须证明自己在布局规划之外也能做到同等水平或更优。除一般产品主张外,没有先进节点覆盖范围的公开证据。

这些行聚焦 AI 辅助芯片设计软件特有的运营执行风险,而非泛泛的 SaaS 创业风险。

[CR008, CR010, CR012, CR017, CR018, CR020]

7.3 出口管制和集中的半导体供应链可能推迟或压窄商业化路径

Ricursive 所处的价值链位置里,合规和供应链问题不是背景噪音。BIS 指引、法律分析和当前报道都指向一种监管格局:先进芯片、相关服务、远程用户,甚至晶圆代工产能转移,都已经成为需要承销的政策问题。2026 年 1 月的规则变化为部分对中国和澳门出口引入了更灵活的路径,但代价是更严格的认证、KYC、测试和终端用户披露负担。2026 年 6 月的澄清随后重申,中国母公司在中国境外的子公司仍在合规边界内。与此同时,生态的制造侧仍高度集中。Trade.gov 称,台湾仍掌握超过 60% 的晶圆代工收入和超过 90% 的领先制程制造;GAO 和 SEMI 则显示,美国多元化正在推进,但时间尺度按多年甚至十年计算。对于一家未来可能需要跨境获得晶圆代工、封装、云和客户访问的创业公司,这意味着即使设计软件本身运行良好,商业节奏也可能被政策摩擦和瓶颈供应商卡住。[CR024, CR025, CR026, CR027, CR028, CR029]

监管 / 法律风险登记表
风险当前公开证据可能性影响缓释成熟度剩余敞口尽调路径
出口管制与远程访问合规负担BIS、Finnegan、Mayer Brown 和 MoFo 都显示,AI 芯片交易现在要求在硬件和服务层执行 KYC、远程用户披露、测试和国家筛查。低-中筛查栈薄弱时,收入规模化前就可能卡住销售或产生执法风险。审查律师备忘录、筛查工作流、受限方检查和产品分类文件。
中国关联客户或子公司敞口2026 年 6 月指引重申,总部在中国的公司即使位于中国境外,仍受到先进 AI 芯片许可限制。中高国际客户或云伙伴可能带来隐藏的管辖权和母公司风险。将每个客户、转售商和计算伙伴映射到母公司所有权和国家敞口。
代工厂产能转移认证风险2026 年 1 月规则要求申请人证明出口不会把全球代工厂产能从美国终端用户处转走。初创公司可能难以支撑或影响此类认证所需证据。评估商业模式是否会依赖交易对手把受控硬件运入敏感市场。
远程访问与 AI-as-a-service 规则演进Mayer Brown 和 MoFo 都强调,远程终端用户和 AI-as-a-service 流程现在已进入合规讨论。中高软件交付和云访问可能成为受监管的分发渠道,而不再是中性基础设施。对照当前 BIS 指引测试产品架构,并维持季度律师复核。
公司专属合规准备度不公开公开记录没有显示 Ricursive 的出口管制项目、审计节奏或合规负责人。中高治理和流程深度得到验证前,剩余法律风险仍然偏高。索取出口管制负责人、培训记录和任何第三方合规评估。

严重性排序反映合规摩擦在任何明确执法行动前拖慢商业化的可能性。

[CR024, CR025, CR027, CR028, CR029, CR030]
合作伙伴 / 依赖风险登记表
依赖项交易对方角色集中度失效情景严重性缓释措施剩余风险
领先制程代工产能TSMC 与台湾生态先进客户设计的制造路径极高商业证明依赖一个围绕台湾和少数先进节点供应商高度集中的生态。使用多项目晶圆班车,培养替代节点策略,并避免过早承诺制造时间表。Ricursive 无法独自分散地缘政治和节点集中风险。
先进封装、掩模和联盟服务TSMC 与专业合作伙伴把设计胜利转化为可制造硅片由于封装、掩模或服务准入无法按对创业公司友好的条款获得,设计胜利停滞。预先谈好合作伙伴路径,把范围聚焦在设计工具,而不是完整制造承诺。封装和掩模依赖仍可能拖慢客户证明。
客户工作流集成Cadence、Synopsys、Siemens 主导的环境进入既有设计组织的必要条件潜在客户认为从现有流程切换的成本过高。定位为增强或互操作既有流程,而不是要求彻底替换。现有厂商可以捆绑相邻产品并守住客户。
跨境合规生态代工厂、云厂商、渠道合作伙伴和客户决定设计和算力能否跨司法辖区流动中高合作伙伴的国家敞口或远程用户模式制造隐藏合规障碍。把出口筛查纳入合作伙伴准入和合同条款。每增加一个合作伙伴和地域,负担都会上升。
面向创新者的小批量制造准入国内外代工厂支持原型开发或创业客户所必需中高面向创业公司的原型路径太慢或太贵,无法支撑早期客户。中高采用仿真、模拟和 MPW 策略,同时优先服务已有硅片流程的客户。在规模改善之前,一些有吸引力的客户细分可能仍够不到。

这份登记表强调的是即便底层软件展现技术潜力,仍可能阻断客户转化的依赖项。

[CR013, CR014, CR026, CR031, CR032, CR036]
FR003: 依赖图

关键外部依赖塑造 Ricursive 从研究叙事走向商业设计平台的路径。

[CR013, CR022, CR027, CR031, CR036, CR042]

7.4 客户采用风险仍高,因为估值跑在可见商业证明之前

公司的融资能力是缓释资产,但如果采用滞后,也会让下行更锋利。公开材料尚未识别付费客户、收入或部署案例。叙事反而围绕创始人履历、AlphaChip 历史和投资人信念搭建。在软件品类里,这种状态短期内可以接受;但芯片设计平台面对更长的验证循环、更高的切换成本,也必须更深地接入客户工具链、晶圆代工和封装计划。牵引力最终需要达到的门槛因此更高。同一组供应链证据既验证了市场的重要性,也说明采用为什么可能很慢:创业公司获得晶圆厂访问很难,低量制造并不是为小型创新者设计,大客户也已经与现有 EDA 厂商建立关系。换句话说,Ricursive 已经清楚验证了投资人需求,但尚未公开验证客户需求。在公开客户证明出现之前给出 $4 billion 估值,留给基准、首批设计胜利或合规驱动商业化延误的容错空间很小。[CR003, CR004, CR006, CR023, CR031, CR032]

FR002: 风险传导图

Ricursive 的主要风险如何传导到采用、时间线、利润率、融资和估值。

[CR023, CR028, CR031, CR042, CR043, CR045]

7.5 人才集中、公开组织深度薄、证据质量缺口让剩余风险居高不下

Ricursive 的公开形象刻意保持集中:小型精英团队、两位非常出色的创始人,以及一组很窄的开放职位。最早期研究阶段,这可以是优势;但当公司试图在一个同时需要先进算法研究、验证、安全、出口管制尽调、生态伙伴关系和企业客户管理的市场中商业化时,它会变成风险。Oregon State 的劳动力报告和 Embedded 的行业分析都强化了这一点:验证和专业人才在整个行业都稀缺,Ricursive 招人面对的是结构性紧张市场,而不只是普通竞争市场。公开招聘页显示,EDA 算法、RTL 与设计验证、基础设施、研究和安全都有开放需求,但看不到组织冗余、客户面领导层或合规责任归属。叠加更广泛的证据质量问题——最详细的正面材料大多来自公司和投资人——剩余风险高于单看技术叙事时的水平。公司很可能执行成功,但公开证据基础仍要求投资人基于信任承销几项任务关键能力。[CR018, CR019, CR039, CR040, CR041, CR042]

人员 / 执行风险登记表
角色或职能依赖或缺口发生可能性严重性缓释措施尽调路径
创始人 / 技术愿景公开叙事高度集中在 Goldie 和 Mirhoseini 身上。强创始人-市场匹配和深度既往协作,降低了基础执行不确定性。要求披露接班覆盖、直接下属,以及谁负责日常产品和商业执行。
验证专家全行业短缺叠加客户要求提高,使验证人才很难招聘。智能体工具可能提升个人产出,公司也在招聘该职能。审查验证岗位的招聘漏斗、填补周期和承包商依赖。
安全与合规责任公开信息只显示一个创始安全岗位,而出口管制负担正在扩大。中高管理层似乎意识到需求,并在早期招聘。确认今天谁负责产品安全、出口合规和客户数据治理。
商业和客户成功覆盖公开材料未显示深厚的商业化或解决方案工程团队。中高强投资人可以帮助招聘商业负责人。要求面向客户的组织架构、首个设计胜利支持模型和企业部署手册。
小型精英团队的组织冗余窄团队可以快速推进,但也会制造单点故障。中高中高已融资本提供空间,可在收入规模化前补上冗余。审查离职情况、关键人留任包,以及关键领域之间的重叠覆盖。

重点是执行带宽和组织冗余,而不是泛泛的招聘难度。

[CR018, CR019, CR039, CR040, CR041, CR042]

7.6 展示材料

Chapter 08

08估值

8.1 融资背景,以及为什么 $4B 标记偏激进

Ricursive Intelligence 从 2025 年 12 月约 $750 million 的种子轮估值,跃升到 2026 年 1 月 Series A 轮投后估值 $4 billion;彼时公司公开露面才几个月。在 2025-2026 年前沿 AI 市场里,这种跃升并非不可能,但即便按当前巨额融资轮标准也异常激进。现有证据显示,投资人押注的是创始人与愿景:Anna Goldie 和 Azalia Mirhoseini 凭 AlphaChip 与 Google TPU 工作拥有罕见可信度,公司瞄准 AI 基础设施里的真实瓶颈,本轮也迅速由一批顶级 AI 和半导体投资人联合完成。与此同时,公开记录没有披露收入、ARR、毛利率、客户数量或具名付费设计项目。因此,这笔融资定价的是未来平台相关性,而不是已证明的商业产出。向 $4 billion 投后估值投入 $300 million 新股,也意味着新钱稀释只有约 7.5%,本轮把价格预期向上重置,却没有带来通常支撑耐久后期基准所需的运营透明度。[CV001, CV002, CV003, CV004, CV005, CV006]

建议摘要表
维度评估决策含义
建议观察 / 继续研究在承销买入案例前,等待商业证明。
信心创始人和市场逻辑可信,但公开运营证明薄。
风险评级执行、商业化和估值支撑风险仍然很大。
估值立场偏高$4B 标记更多定价未来成功,而不是已披露的当前表现。
当前锚点2026 年 1 月投后估值 $4B 的 Series A 轮把它当作最新的市场出清私人价格,而不是已证明的内在价值。
反向视角执行能力相对现有厂商错配技术潜力未必能转化为经过基准验证的商业优势。
上调触发项具名付费客户加经过基准验证的设计胜利会提高对该估值由真实需求支撑的信心。
主要下行触发项下一轮融资前仍无收入证明或基准数据偏弱会提高叙事压缩或后续平轮 / 下轮融资的风险。

该建议明确对价格和证据敏感;它不是对创始人质量的泛泛判断。

[CV001, CV024, CV025, CV036, CV040, CV045]
投资逻辑 / 反向逻辑表
维度乐观逻辑反向逻辑什么会改变判断
创始人与技术可信度AlphaChip 背景和稀缺人才密度,值得给予溢价关注。光有声望并不能证明 Ricursive 在生产环境中胜过商业 EDA 工作流。相对现有厂商基线的独立基准数据。
市场需求AI 实验室和超大规模云厂商明确需要更快的定制硅片迭代。真实市场瓶颈并不保证 Ricursive 能拿到有吸引力的经济收益。多个买方的签约付费项目和扩张证据。
融资质量顶级投资人快速联合完成 $335M 总融资。估值 5.3x 跳升发生在收入披露之前,价格可能更多反映稀缺性而非牵引力。与运营披露挂钩的新融资或老股交易定价。
竞争位置Ricursive 可能成为芯片制造商和云实验室的战略赋能层。Synopsys 和 Cadence 已经推出带客户引用的 AI 优化工具。证明 Ricursive 在有意义设计上交付更好的达成时间或 PPA。
技术叙事递归式 AI-硬件共同演化,是一个有力的长期故事。公开反向报道称,AlphaChip 式优越性仍有争议且算力密集。在当前工业工作负载上获得可复现的第三方验证。
退出逻辑稀缺性可能支撑又一轮溢价私募融资或战略合作。缺少已披露收入、利润率和客户集中度,近期 IPO 支撑偏弱。数据室级别披露,使 Ricursive 能与上市同业比较。

反向逻辑聚焦估值支撑和商业化证据,而不是否认 AI 芯片设计自动化的重要性。

[CV005, CV014, CV015, CV025, CV026, CV029]
FV001: 推荐逻辑

从稀缺创始人和市场需求,推导到当前观察 / 继续研究建议的决策链。

这条路径是分析框架,不是机械流程;它把主要估值驱动因素压缩成一条可提交投委会的建议路径。

[CV005, CV015, CV024, CV025, CV036, CV045]

8.2 可比公司组和市值收入倍数代理

对 Ricursive 最干净的外部框架不是直接找创业公司可比,而是混合使用上市 EDA、半导体和前沿 AI 参照点。Synopsys 和 Cadence 重要,因为它们已经把 AI 辅助芯片设计工具卖进真实客户工作流。NVIDIA 和 AMD 重要,因为它们锚定了投资人当前愿意为 AI 算力领导者支付的价格,尽管它们是规模大得多的硬件企业。2026 年 6 月 12 日的市值和收入快照意味着,Synopsys 收入倍数约 10.9x,Cadence 约 19.2x,NVIDIA 约 23.0x,AMD 约 24.1x。这些倍数很高,但对应的是披露收入、庞大安装基础和已验证产品市场匹配的公司。把同样代理倒推到 Ricursive,可以看出当前价格需要多少商业实质来支撑。根据采用的可比视角不同,$4 billion 估值大约需要 $166 million 到 $367 million 的年收入。没有任何引用的 Ricursive 来源披露过接近这一基准的内容,因此当前标记本质上是对创始人、技术叙事和被感知的战略可选性的稀缺性溢价。私有前沿 AI 同业确实显示,$4 billion 或以上的纸面估值可以很早出现,但这些标记仍不能替代收入支撑。[CV011, CV012, CV013, CV014, CV018, CV019]

乐观 / 基准 / 悲观情景表
情景概率信号估值区间关键假设主要失效模式
悲观30%$2.5B-$3.25BRicursive 赢得关注,但没有足够经基准验证或付费牵引来支撑 2026 年 1 月的溢价。下一轮融资需要围绕证据而非稀缺性重新定价。
基准50%$3.5B-$4.5B公司把投资人热情转化为早期商业项目,但仍缺少完整运营披露。商业证明到来的速度慢于招聘和算力开支爬坡。
乐观20%$5.0B-$6.0BRicursive 在重要客户项目上证明可量化压缩设计周期并提升 PPA,使平台具备战略稀缺性。在 Ricursive 扩大收入规模前,现有厂商复制其功能集。
概率加权中心100%~$3.7B-$4.1B只有基准情景在未来 12-18 个月开始兑现,当前轮次才大致说得通。如果缺少里程碑,加权中心会漂到上一轮标记之下。

区间是分析师情景框架,不是公司指引;Ricursive 尚未披露收入或利润率输入,因此这些区间保留不确定性。

[CV023, CV037, CV038, CV039, CV043, CV044]
可比估值表
可比对象状态 / 日期价值 / 指标隐含收入倍数或标记相关性局限
Ricursive 种子轮私人 / 2025 年 12 月$750M 估值;$35M 种子轮基础前轮标记显示 2026 年 1 月轮次在短窗口内上调了多远。种子轮标记没有同步披露公开运营指标。
Ricursive Series A 轮私人 / 2026 年 1 月$4.0B 投后估值;$300M 轮次最新市场出清私人价格当前入场纪律的主要锚点。仍缺少公开收入、利润率或客户披露。
Synopsys上市 / 2026 年 6 月$86.91B 市值;$8.00B TTM 收入~10.9x 市值 / 收入与 AI 芯片设计直接相关的 EDA 现有厂商。大型、成熟、多元化上市公司。
Cadence上市 / 2026 年 6 月$106.17B 市值;$5.52B TTM 收入~19.2x 市值 / 收入最接近的上市 AI-EDA 工作流可比组。同样成熟、全球化,且已经商业化。
NVIDIA上市 / 2026 年 6 月$4.969T 市值;$215.93B TTM 收入~23.0x 市值 / 收入AI 基础设施稀缺性的上限代理。硬件平台领导者,不是创业软件工具可比对象。
AMD上市 / 2026 年 6 月$834.16B 市值;$34.63B TTM 收入~24.1x 市值 / 收入另一个高速增长无晶圆厂模式下的 AI 硅片代理。规模仍远大于 Ricursive,披露也多得多。
Unconventional AI私人 / 2025 年 12 月$4.5B 估值;$475M 种子轮前沿 AI 基础设施稀缺性的叙事同业显示当前市场存在数十亿美元种子轮标记。不是直接的芯片设计自动化可比对象。
Humans&私人 / 2026 年 1 月$4.48B 估值;$480M 种子轮前沿 AI 账面定价的叙事同业证实投资人有时会为团队和叙事支付极端溢价。对 Ricursive 最终变现说明有限。

上市公司收入代理使用市值和 TTM 收入快照。私人创业公司行是估值参考点,不是基于倍数的可比对象。

[CV001, CV002, CV018, CV019, CV020, CV021]
FV002: 估值敏感性

按选定上市公司收入倍数反推,Ricursive 需要达到多少隐含年收入,才撑得住 $4B 估值。

数值只是用 $4,000M 除以所选倍数得到的隐含收入,并非 Ricursive 管理层指引。

[CV018, CV019, CV020, CV021, CV022, CV023]

8.3 反向情景、执行错配和情景框架

反向情景不是 Ricursive 缺少可信技术团队,而是商业估值可能跑在可复现差异化之前。New Scientist 记录了外部对 AlphaChip 风格主张的严肃批评,包括公共证据尚未显示其相对于专家设计师或商业工具有稳定超额表现,以及强化学习方法可能需要多得多算力的质疑。与此同时,Synopsys 和 Cadence 已经在营销生产级 AI 优化产品,Cadence 到 2026 年初仍在扩展其 AI 自动化栈。这意味着 Ricursive 不仅要证明 AI 能帮助芯片设计,还要证明自家系统能创造足够增量的速度、功耗性能面积改进或工作流自动化,从而把预算从现有厂商那里拉走,或成为它们的战略层。悲观情景因此围绕执行错配展开:创始人叙事很强,人才和算力投入很高,但付费部署或经基准验证结果转化缓慢。基准情景大体维持当前估值,因为前沿 AI 稀缺性和战略兴趣仍然真实。乐观情景则需要能被买家而不只是投资人看懂的可衡量商业牵引力、伙伴集成和技术胜利。[CV007, CV008, CV009, CV010, CV014, CV015]

投资逻辑失效和终止触发项表
触发项阈值 / 事件对投资逻辑的传导行动含义
相比在位厂商的基准差距在客户实际设计上,相比 Synopsys/Cadence 工作流没有清晰改进削弱核心主张:Ricursive 是差异化平台,而不是名校光环项目。估值立场转向悲观情景,并要求大幅压低入场价格。
没有具名付费客户下一轮融资仍没有客户名称、付费试点或收入区间显示商业证明落后于资本投入。建议维持在继续研究或更低。
技术质疑持续第三方复现仍未显示 AlphaChip 式的清晰优势提高「叙事跑在可复现优势前面」的概率。将公司视为实验性基础设施研发,而不是已规模化的软件平台。
政策摩擦上升出口管制或生态规则限制跨境 AI 芯片项目可能放慢获客,并收窄合作伙伴集合。提高所需安全边际,并缩短投资判断周期。
条款包袱显现Series A 优先权、棘轮条款或治理权显著压低普通股上行空间会让表面的 $4B 估值在经济性上不那么有吸引力。作出任何承诺前,先从股权结构表重建回报测算。

每个触发项都可能改变概率加权估值区间,或改变按当前估值买入的经济吸引力,因此都值得单独跟踪。

[CV017, CV033, CV036, CV037, CV040, CV045]
FV003: 估值 / 回报区间

基于证据质量和执行里程碑,给出 Ricursive 的悲观、基准、乐观估值走廊,单位为十亿美元。

情景区间为分析师估计,既保留不确定性,也围绕最新融资估值锚定。

[CV037, CV038, CV039, CV043, CV044, CV045]
FV004: 投资 KPI

一张投委会式评分卡,覆盖最能决定 Ricursive 是否配得上高于叙事估值的关键维度。

分数是基于有来源证据形成的分析判断,并非公司披露,也不是管理层给出的量化评级。

[CV014, CV024, CV025, CV031, CV036, CV045]

8.4 建议、入场纪律和最终尽调要求

今天最可防守的判断是观察 / 继续研究,置信度中,风险高,估值立场偏高。如果 Ricursive 证明更快设计周期、更好算力效率,并在主要芯片项目中跑出可重复客户采用,它可能具备战略重要性。但今天的公开证据仍缺少把估值故事变成可承销投资案例的输入:收入、客户证明、利润率结构、相对于现有工作流的基准性能,以及 $300 million Series A 中嵌入的权利。价格敏感性很重要,因为 2026 年 1 月这一轮已经把相当一部分上行叙事资本化。没有新的运营证据,支付高于当前 $4 billion 基准的价格,等于只承销声望和稀缺性。闸门式尽调项目很直接:证明谁在付费、为何付费、Ricursive 相比 Synopsys 和 Cadence 基线带来什么技术改进,以及公司能多快把招聘和算力建设转化为商业收入。在这组证据可见之前,支持另一轮私募融资或战略伙伴关系,比支持近期 IPO 式估值框架更容易。[CV023, CV024, CV025, CV032, CV038, CV039]

最终尽调问题表
主题缺失证据重要性尽调路径
收入模型当前收入、软件 / 许可 / 服务属性,以及任何 ARR 口径没有收入形态,公开可比公司测算只能粗略代理。要求提供收入拆解、定价模型,以及确认收入与签约收入明细。
客户证明具名付费客户、项目规模、生产或试点状态、续约路径估值故事必须从战略兴趣转成付费采用。询问头部设计合作伙伴、合同阶段和用例结果。
基准结果相比在位工作流,实测布局时间、验证吞吐量和 PPA 改进这是技术优势转商业价值的核心证明。要求第三方基准包和客户推荐。
毛利率和算力成本训练 / 推理的单位经济、服务组合和交付模式如果算力或服务负担压住利润率,就很难支撑软件式倍数。复核队列级毛利率和算力 COGS 假设。
Series A 条款优先股堆叠、董事会权利、按比例跟投结构,以及任何投资人保护经济吸引力可能与表面估值明显不同。获取股权结构表、股份购买协议和主要投资人侧信。
现金跑道和招聘计划现金消耗、招聘速度和算力资本开支承诺帮助判断本轮资金是在支持证明,还是只是在延长实验。要求运营计划、烧钱桥和算力基础设施承诺。

买方若要在 2026 年 1 月投后估值基准之上显著承销,至少需要拿到这些尽调材料。

[CV024, CV029, CV031, CV032, CV045, CV046]

免责声明

本尽调报告由 AI 研究智能体基于截至 2026-06-13 可获得的公开资料生成,不构成投资建议。Ricursive Intelligence 是一家私人公司,公开披露有限;任何投资决定都应结合管理层、客户、法律和投资人材料再验证。

证据索引

结论
编号陈述可信度来源
CO001 Ricursive publicly launched on 2025-12-02 with a $35 million seed round at a $750 million valuation led by Sequoia. SO002, SO010, SO011
CO002 Ricursive describes itself as a frontier AI lab building self-improving systems that start with chip design. SO001, SO002
CO003 Ricursive says its platform uses AI to accelerate and optimize every stage of semiconductor design. SO002, SO011
CO004 Anna Goldie is Ricursive's co-founder and CEO. SO002, SO004
CO005 Azalia Mirhoseini is Ricursive's co-founder and CTO. SO002, SO005
CO006 Independent launch coverage and the current jobs page place Ricursive in Palo Alto, California. SO009, SO011, SO012
CO007 Ricursive is a private Series A company less than one year past public launch as of 2026-06-13. SO003, SO004
CO008 On 2026-01-26 Ricursive announced a $300 million Series A at a $4 billion post-money valuation led by Lightspeed. SO003, SO004, SO012
CO009 Total capital raised is reported as $335 million after the seed and Series A. SO001, SO004, SO005
CO010 Ricursive's official site says it is backed by Sequoia, Lightspeed, DST, and NVentures and is scaling a small, elite team. SO001
CO011 No retained public source names a paying customer, discloses revenue, or gives a customer count. SO001, SO003, SO005
CO012 Nature's 2021 AlphaChip paper says reinforcement-learning-based chip floorplanning can generate layouts in under six hours with metrics comparable or superior to human designs. SO013
CO013 Multiple Ricursive-linked sources say AlphaChip has been used across four generations of Google's TPUs and by external semiconductor companies. SO001, SO003, SO006
CO014 New Scientist reported in 2024 that Google DeepMind described AlphaChip as having designed three TPU generations and that independent experts said public proof of superiority was insufficient. SO014
CO015 Google's circuit_training repository says AlphaChip is an open-source framework reproducing the Nature 2021 methodology and is used across Alphabet and outside it. SO015
CO016 Felicis says Goldie and Mirhoseini began exploring the underlying thesis together in 2018. SO008
CO017 Sequoia's podcast page says AlphaChip reduced chip floorplanning from months to hours. SO007, SO013
CO018 Lightspeed says leading-edge chip design often takes two to three years and hundreds of millions of dollars. SO006
CO019 Synopsys DSO.ai and Cadence Cerebrus show AI-assisted chip design is already a commercial category. SO016, SO017, SO018
CO020 TechCrunch says Ricursive is building AI tools that design chips rather than manufacturing chips itself. SO005
CO021 TechCrunch says Ricursive's target customers include chipmakers such as Nvidia, AMD, Intel, and other electronics companies needing custom chips. SO005
CO022 Ashby listed seven open onsite Palo Alto roles across EDA, LLM infrastructure, software infrastructure, RTL and design verification, research, and security on 2026-06-13. SO009
CO023 Ricursive's site and Lightspeed both emphasize a talent base drawn from Google DeepMind, NVIDIA, Apple, Cadence, Anthropic, and xAI. SO001, SO006
CO024 The disclosed investor set includes Lightspeed, Sequoia, DST Global, NVentures, Felicis, 49 Palms, Radical, and others. SO003, SO004, SO008, SO012
CO025 Ricursive's valuation stepped up about 5.3x from $750 million at seed to $4 billion at Series A in under two months. SO002, SO003
CO026 The Series A proceeds are earmarked for team expansion and compute infrastructure. SO003, SO010
CO027 The launch announcement said seed proceeds would fund AI research, compute infrastructure, and early enterprise adoption. SO002, SO010
CO028 Sequoia says Ricursive's business model is to make the industry designless by letting companies create custom silicon without in-house design teams. SO007
CO029 Ricursive's official site says team members have hands-on experience developing Gemini, Claude, Grok, and TPUs. SO001
CO030 Google TPUs, AWS Trainium, and Microsoft Maia show hyperscalers already deploy first-party AI chips to improve AI economics. SO019, SO020, SO021
CO031 SEMI forecasts front-end fab equipment spending to reach $130 billion in 2026 as AI-related demand keeps rising. SO026
CO032 BIS's EAR page and May 2025 policy statement show some advanced-computing chip and AI-model-training activities can require U.S. export authorization. SO022, SO023
CO033 CSIS says U.S. semiconductor export controls rely on allied chokepoints and have continued to expand since 2022. SO024
CO034 Morrison Foerster says 2026 enforcement risk in AI chips extends beyond manufacturers to forwarders, financiers, and data-center operators. SO025
CO035 Ricursive's regulatory exposure is indirect but material because its likely customers and compute partners operate inside a shifting export-control regime. SO022, SO024, SO025
CO036 All retained 2026 company and media sources keep Goldie and Mirhoseini in the CEO and CTO roles, showing no public leadership churn since launch. SO001, SO003, SO005
CO037 Retained public sources do not disclose a public board roster or a broader executive directory beyond the founders. SO001, SO003, SO005
CO038 TechCrunch says VC interest centered heavily on founder pedigree and that many investors had previously tried to hire the founders. SO005
CO039 Ricursive's platform is described as pre-commercial or early-enterprise rather than broadly deployed with named design wins. SO002, SO005
CO040 The launch release says Ricursive intended to work with hyperscale partners, but no partner names are disclosed in retained public sources. SO002, SO003
CO041 TechCrunch says Ricursive's platform will use LLMs and handle work from component placement through design verification. SO005
CO042 Converge Digest and the launch release describe Ricursive as a full-stack AI platform spanning layout, optimization, verification, and architecture exploration. SO002, SO011
CO043 Sequoia says the founders prefer synthetic data to scale some training while keeping customer data private and siloed. SO007
CO044 Ricursive's public narrative is explicitly long-horizon and AGI-oriented rather than only a near-term EDA efficiency pitch. SO001, SO002, SO008
CO045 No debt or credit facility is disclosed in the retained seed and Series A sources. SO002, SO003, SO004
CM001 Ricursive is positioning itself as an AI company for semiconductor design rather than as a chip manufacturer or foundry. SM001, SM002, SM003
CM002 Ricursive says its product ambition is a full-stack chip-design platform that starts with layout and extends across the broader design workflow. SM001, SM003, SM005
CM003 TechCrunch reports that Ricursive intends to handle everything from component placement through design verification. SM003
CM004 Ricursive and its backers frame the company as an enabler of custom-silicon creation rather than as a seller of finished AI accelerators. SM001, SM002, SM005
CM005 Synopsys DSO.ai and Cadence Cerebrus show that AI-assisted chip-design automation is already a commercial software category inside broader EDA workflows. SM007, SM008, SM009
CM006 Synopsys DSO.ai is positioned as an autonomous AI application for chip design that uses reinforcement learning to search very large solution spaces for power, performance, and area optimization. SM007, SM008
CM007 Cadence Cerebrus is positioned as an AI-driven automated chip-design flow optimizer that uses full-flow reinforcement learning and LLM capabilities to improve PPA and engineering productivity. SM009, SM010
CM008 Nature describes chip floorplanning as an engineering task that historically required months of intense effort by physical-design engineers. SM011
CM009 Nature reports that its reinforcement-learning method generated floorplans in under six hours that were superior or comparable to human output on the reported designs. SM011
CM010 New Scientist reports that independent researchers say public evidence still does not prove AlphaChip outperforms expert humans or commercial software on current benchmark designs. SM012
CM011 Lightspeed says the most performant silicon still takes large teams two to three years and hundreds of millions of dollars to design. SM005
CM012 AWS says Synopsys DSO.ai can identify design optimizations in weeks rather than months by exploring large design spaces automatically. SM008
CM013 AWS gives concrete DSO.ai examples including 20 percent better leakage power and smaller-area outcomes on specific workloads. SM008
CM014 Forbes says semiconductor AI tooling has already delivered roughly 10x productivity gains on relatively narrow tasks such as floor-plan optimization. SM010
CM015 Ricursive targets companies that make electronics and need chips, which puts fabless chipmakers, systems companies with custom ASIC roadmaps, and hyperscaler silicon teams inside its buyer universe. SM003, SM002, SM023
CM016 AWS markets Trainium as a purpose-built AI chip for high-performance training and inference at scale. SM013
CM017 Google says TPUs are custom-designed accelerators used for Gemini and other Google AI applications. SM014
CM018 Microsoft says Maia 200 is its inference accelerator built on TSMC 3nm and delivers 30 percent better performance per dollar than the latest generation hardware already in its fleet. SM015
CM019 The presence of Trainium, TPU, and Maia shows that hyperscalers are now sustaining a real custom-silicon race rather than treating AI chips as a one-off experiment. SM013, SM014, SM015
CM020 SEMI says front-end fab-equipment spending should reach 110 billion dollars in 2025 and 130 billion dollars in 2026 as AI-related chip demand drives capacity expansion. SM016
CM021 That SEMI fab-equipment forecast is an adjacent downstream capex signal rather than Ricursive’s addressable software market. SM016, SM001, SM003
CM022 Synopsys generated about 8.00 billion dollars of revenue in 2025 and Cadence generated about 5.29 billion dollars in 2025, creating an observable 13.29 billion dollar upper-bound proxy for the broad EDA and IP software pool. SM019, SM020
CM023 The same combined revenue pool is about 13.52 billion dollars on a 2026 trailing-twelve-month basis, suggesting the broad EDA software ceiling is growing but still far below semiconductor capex or AI-compute revenue pools. SM019, SM020, SM016
CM024 Cadence and Synopsys together were worth roughly 193.08 billion dollars in public market capitalization in June 2026, which is useful valuation context but not a spend-based TAM measure. SM021, SM022
CM025 The monetized AI chip-design automation segment is narrower than the broad EDA pool because public category proof today centers on PPA, floorplanning, and flow optimization rather than total workflow replacement. SM007, SM008, SM009, SM011
CM026 A conservative near-term annual spend range for AI chip-design automation is about 0.5 to 1.5 billion dollars if adoption remains concentrated in point-tool workflows such as floorplanning and PPA optimization. SM007, SM008, SM009, SM011
CM027 A base-case near-term SAM of roughly 2.0 to 5.0 billion dollars is plausible only if advanced custom-silicon teams adopt automation across multiple stages from placement into verification and signoff. SM003, SM005, SM007, SM009
CM028 The broad 13-plus-billion-dollar incumbent revenue pool is best treated as Ricursive’s outer ceiling rather than as its realistic near-term SAM because it already includes legacy tools, IP, and workflows Ricursive has not yet displaced. SM019, SM020, SM003, SM005
CM029 The status-quo substitute for Ricursive is a labor-heavy incumbent EDA flow where engineering teams iterate manually inside established tools until they reach design closure. SM005, SM008, SM009
CM030 The closest adjacent substitutes are incumbent AI modules from Synopsys and Cadence rather than foundries, fab-equipment vendors, or AI-chip manufacturers. SM007, SM008, SM009, SM016
CM031 The most likely initial budget owners are CAD, physical-design, or silicon-platform leaders, with economic sponsorship escalating to vice presidents of engineering or silicon when the platform touches multiple workflow stages. SM003, SM008, SM009
CM032 The natural adoption path is to win a benchmark or pilot on one block, then expand into signoff, verification, and broader program deployment after engineers trust the results. SM003, SM008, SM009, SM010
CM033 The strongest growth driver is the custom-silicon arms race, because hyperscalers and advanced chip teams gain disproportionate value from shortening a design cycle that currently lasts years. SM005, SM013, SM014, SM015
CM034 A second growth driver is that incumbent tools have already normalized the idea that AI can improve chip-design productivity and PPA. SM007, SM008, SM009, SM010
CM035 The main adoption constraints are flow-integration risk, switching cost into entrenched EDA stacks, and customer trust about whether automation generalizes beyond narrow tasks. SM008, SM009, SM010, SM012
CM036 Ricursive has not publicly disclosed named production design wins, public pricing, or verification benchmarks, so valuation still depends more on founder pedigree and category promise than on demonstrated market penetration. SM003, SM004, SM023, SM024, SM025
CM037 BIS and Morrison Foerster indicate that advanced-semiconductor export controls now create real enforcement and customer-mix risk across the AI-chip ecosystem. SM017, SM018
CM038 Ricursive therefore belongs inside a narrow but high-value AI chip-design automation layer within EDA, not inside the much larger buckets of semiconductor manufacturing spend, fab equipment, or AI-chip revenue. SM001, SM003, SM016, SM020
CM039 The most defensible three-layer sizing logic is a broad 13.29 to 13.52 billion dollar incumbent-software ceiling, a narrower 2.0 to 5.0 billion dollar multi-stage automation SAM, and a 0.5 to 1.5 billion dollar near-term point-tool beachhead. SM019, SM020, SM007, SM009
CM040 The buyer journey runs from technical benchmark credibility to pilot deployment to workflow standardization, which means Ricursive’s commercial timing is gated by proof, not just by TAM rhetoric. SM003, SM008, SM009, SM012
CP001 Ricursive describes itself as a frontier AI lab building self-improving systems that start with chip design. SP001, SP024
CP002 Ricursive's Series A materials and launch materials frame the product as a next-generation platform intended to accelerate and optimize every stage of the semiconductor design process. SP002, SP024
CP003 Lightspeed argues that the most performant silicon typically takes large teams two to three years and hundreds of millions of dollars to design. SP003
CP004 TechCrunch reports that Ricursive is building AI tools that design chips rather than manufacturing the chips themselves. SP004, SP023
CP005 Synopsys positions DSO.ai as autonomous RTL-to-GDSII full-flow optimization that reduces design time and improves design quality across logical and physical domains. SP005, SP006
CP006 AWS says DSO.ai uses reinforcement learning to search enormous chip-design spaces, improve PPA, and identify optimization opportunities in weeks rather than months. SP006, SP005
CP007 Cadence describes Cerebrus as an AI-driven automated approach to chip-design flow optimization with generative AI features and distributed-compute support. SP007, SP008
CP008 Forbes reported in February 2026 that Cadence launched the ChipStack AI Super Agent as an agentic workflow for automating chip design and verification with up to 10x productivity improvements. SP008, SP007
CP009 As of June 2026, Synopsys had a public market-cap proxy of $86.91 billion. SP015
CP010 Synopsys's TTM revenue proxy was $8.00 billion in 2026. SP016
CP011 As of June 2026, Cadence Design Systems had a public market-cap proxy of $106.17 billion. SP017
CP012 Cadence's TTM revenue proxy was $5.52 billion in 2026. SP018
CP013 Ricursive and partner sources say AlphaChip has been adopted across four TPU generations and by external semiconductor companies. SP002, SP003, SP025
CP014 TechCrunch and New Scientist describe the publicly cited AlphaChip deployment record as three TPU generations and note that independent experts dispute whether public evidence proves superhuman performance against expert designers or commercial software tools. SP004, SP010
CP015 Google's circuit_training repository is an open-source framework for generating chip floorplans with distributed deep reinforcement learning and it reproduces the Nature 2021 methodology. SP011, SP009
CP016 Sequoia says AlphaChip reduced chip floorplanning from months to hours. SP025, SP010
CP017 Because the floorplanning lineage is open-source, sophisticated internal teams can reproduce part of the AlphaChip method without buying Ricursive software. SP011, SP009, SP025
CP018 Google says TPUs are custom-designed accelerators for AI workloads and that they power Gemini plus Google AI applications serving more than 1 billion users. SP012
CP019 AWS says Trainium is a purpose-built AI chip focused on delivering the best economics for high-performance AI training and inference at scale. SP013
CP020 Microsoft says Maia 200 delivers three times the FP4 performance of third-generation Amazon Trainium, FP8 performance above Google's seventh-generation TPU, and 30% better performance per dollar than Microsoft's latest-generation fleet hardware. SP014
CP021 The public TPU, Trainium, and Maia pages show that major hyperscalers increasingly answer hardware bottlenecks by building first-party silicon and internal toolchains. SP012, SP013, SP014
CP022 NVIDIA's June 2026 public scale proxies were roughly $4.969 trillion of market capitalization and $215.93 billion of TTM revenue. SP019, SP020
CP023 AMD's public scale proxies were roughly $834.16 billion of market capitalization and $34.63 billion of TTM revenue. SP021, SP022
CP024 For many enterprises, buying merchant accelerators from NVIDIA or AMD is a more immediate substitute than starting a custom-silicon program that would need Ricursive-like tooling. SP019, SP020, SP021, SP022, SP003
CP025 AWS presents DSO.ai as deployable with AWS ParallelCluster, AWS Batch, multiple instance types, multiple job queues, and schedulers such as Slurm. SP006
CP026 Cadence says Cerebrus lets engineers specify design goals, analyze results in a designer cockpit, and reuse optimized AI-driven models for new projects. SP007
CP027 Ricursive's retained public materials do not disclose pricing, packaging, named customers, security attestations, or compliance certifications. SP001, SP002, SP004, SP024
CP028 Because Ricursive pricing is undisclosed and incumbent EDA pricing is also not public in the retained set, public analysis can compare packaging logic but not contract economics. SP001, SP005, SP007
CP029 Ricursive's sharpest public differentiation claim is broader automation ambition: a self-improving full-stack loop rather than a floorplanning-only or optimization-only tool. SP001, SP002, SP003, SP024
CP030 Ricursive says its team is behind AlphaChip, RL-CCD, Insta, and C3PO and has hands-on experience developing Gemini, Claude, Grok, and TPUs. SP001, SP002
CP031 Synopsys and Cadence have multi-billion-dollar revenue bases, entrenched account relationships, and existing workflow footprints that Ricursive does not yet show publicly. SP015, SP016, SP017, SP018, SP001
CP032 Cadence's ChipStack move and Synopsys's autonomous DSO.ai positioning suggest incumbent EDA suites are moving toward broader autonomous or agentic automation. SP005, SP007, SP008
CP033 The New Scientist critique means AlphaChip lineage should be treated as credible but not as settled public proof that Ricursive already outperforms expert human teams or modern EDA tools. SP010, SP009
CP034 No retained public source names a Ricursive design win or published benchmark against DSO.ai or Cerebrus. SP001, SP002, SP004, SP005, SP007
CP035 Public benchmark claims from Maia versus Trainium and TPU show that internal platform vendors continue to push performance-per-dollar improvements that can shrink demand for outsourced design tooling among hyperscalers. SP012, SP013, SP014
CP036 Ricursive's moat therefore has to come from workflow breadth, data feedback loops, and deployment execution rather than from the core macro-placement idea alone. SP001, SP003, SP009, SP011
CP037 There are zero named public Ricursive customers in the retained source set as of 2026-06-13. SP001, SP002, SP004, SP024
CP038 Ricursive's direct commercial rivals are Synopsys DSO.ai and Cadence Cerebrus / ChipStack, while internal build and merchant silicon compete as substitutes for the buyer's job-to-be-done. SP005, SP006, SP007, SP008, SP012, SP013, SP014, SP019, SP021
CP039 The most likely commoditization path is AI capability becoming bundled into incumbent EDA platforms and private internal toolchains while many customers continue buying merchant accelerators instead of designing custom silicon. SP005, SP007, SP008, SP019, SP021
CP040 Competitive verdict: Ricursive looks differentiated on founder pedigree and ambition, but currently disadvantaged on distribution, trust signals, public customer proof, and benchmark evidence. SP001, SP003, SP005, SP007, SP010, SP015, SP017
CP041 Crunchbase News and Data Center Dynamics independently describe Ricursive as a newly launched AI chip-design platform that raised $300 million at a $4 billion valuation within roughly two months of launch. SP026, SP029
CP042 Converge Digest and Semiconductor Digest both describe Ricursive as trying to accelerate semiconductor design through a recursive loop between AI models and chips. SP027, SP028
CP043 Data Center Dynamics and SiliconANGLE both frame Ricursive as an AI chip-design platform rather than a chip-manufacturing company. SP029, SP030
CP044 Multiple trade-press sources frame Ricursive as exceptionally well funded but still very newly launched, reinforcing that public competitive assessment remains pre-customer and pre-benchmark. SP026, SP027, SP028, SP029, SP030
CP045 Broad media repetition across Crunchbase, Converge Digest, Semiconductor Digest, Data Center Dynamics, and SiliconANGLE shows Ricursive has sector mindshare, but not public customer proof, in the current semiconductor and AI press cycle. SP026, SP027, SP028, SP029, SP030
CP046 Synopsys's investor-relations page describes the company as a trusted silicon-to-systems design partner with 35+ years in business, $7+ billion in annual revenue, and 28,000+ employees. SP031, SP016
CP047 AMD's investor page shows that merchant-silicon alternatives continue to invest heavily in AI infrastructure, including more than $10 billion in Taiwan ecosystem investments and recurring 2026 financial disclosures. SP032, SP022
CP048 NVIDIA's investor home frames the company as the world leader in accelerated computing and pairs that positioning with formal quarterly results, SEC filings, and annual-report disclosures, reinforcing the depth of the merchant-silicon substitute. SP033, SP020
CI001 Ricursive publicly positions itself as selling AI tools that design chips rather than manufacturing chips itself. SI001, SI004, SI005
CI002 Public product descriptions say Ricursive is building a full-stack platform spanning layout, optimization, verification, and architecture exploration. SI003, SI005, SI009
CI003 TechCrunch says the company's target customers are chipmakers and electronics companies rather than end users of finished chips. SI005
CI004 No retained public source discloses Ricursive list pricing, usage pricing, or standard contract duration. SI001, SI002, SI003
CI005 No retained public source discloses Ricursive revenue, ARR, GMV, or gross margin. SI001, SI003, SI005, SI006
CI006 Because pricing and customer disclosures are absent, Ricursive's monetization should be underwritten as a potential enterprise software model rather than proven recurring revenue. SI001, SI004, SI005
CI007 Ricursive's official site says the company is backed by $335M and is scaling a small, elite team. SI001, SI005
CI008 Ricursive's public Ashby board lists seven open on-site roles in Palo Alto across EDA, infrastructure, security, and research. SI008
CI009 The current public hiring mix is R&D-heavy because all visible openings are technical or security roles rather than public sales, finance, or customer-success hires. SI008
CI010 Lightspeed says high-performance silicon typically takes two to three years and hundreds of millions of dollars to design, with labor absorbing most semiconductor R&D spend. SI007
CI011 TechCrunch and Sequoia both describe AlphaChip-style workflows as shrinking chip floorplanning from months or a year-plus down to hours. SI005, SI026
CI012 Ricursive's value proposition is labor and time-to-closure compression for chip designers rather than transaction monetization or semiconductor fabrication spread. SI005, SI007, SI009
CI013 TechCrunch reports Ricursive's founders claim AI-hardware co-design could yield almost 10x improvement in performance per total cost of ownership. SI005
CI014 All public job listings are on-site in Palo Alto, indicating a concentrated operating footprint as of the run date. SI008, SI006
CI015 Seven open roles is a small visible hiring footprint relative to the company's disclosed capital base. SI001, SI008
CI016 No retained public source shows a free tier, self-serve checkout flow, or public usage-based price sheet for Ricursive. SI001, SI002, SI003
CI017 Because no public source names customers or design wins, CAC, payback, and sales-cycle efficiency are not observable from the public record. SI001, SI003, SI005
CI018 Ricursive's likely go-to-market motion is high-touch enterprise selling because the workflow is mission-critical and public self-serve pricing is absent. SI005, SI009, SI010, SI012
CI019 Synopsys DSO.ai and Cadence Cerebrus both market AI-driven design optimization aimed at faster design closure and better power, performance, and area. SI010, SI011, SI012
CI020 Forbes reports AI is already used on roughly 20–40% of new leading-edge SoC designs and Cadence markets 10x productivity gains in design and verification. SI012, SI013
CI021 As of June 2026, Cadence and Synopsys carry market capitalizations of $106.17B and $86.91B respectively. SI014, SI016
CI022 CompaniesMarketCap reports 2025 revenue of $8.00B for Synopsys and $5.29B for Cadence. SI015, SI017
CI023 As of June 2026, NVIDIA carries a $4.969T market cap and $215.93B TTM revenue, indicating the scale of AI-accelerator demand around Ricursive's target market. SI018, SI019
CI024 As of June 2026, AMD carries an $834.16B market cap and $34.63B 2025 revenue, providing a second public benchmark for advanced-chip market scale. SI020, SI021
CI025 The nearest public economic analogs for Ricursive are large software and design-tool vendors rather than fabs, which supports software-like upside if the product works. SI014, SI015, SI016, SI017
CI026 Ricursive is still likely to have meaningful internal compute and experimentation expense because its platform couples frontier models with semiconductor-design iteration. SI001, SI005, SI007, SI008
CI027 Official and investor materials repeatedly describe a recursive loop between better AI models and better hardware, implying ongoing model-training and evaluation costs rather than static software maintenance. SI001, SI003, SI007
CI028 Ricursive publicly launched on 2025-12-02 with a $35M seed round at a $750M valuation led by Sequoia. SI002, SI006, SI009
CI029 Ricursive announced a $300M Series A at a $4B post-money valuation on 2026-01-26, less than two months after launch. SI003, SI004, SI024, SI025
CI030 Ricursive and TechCrunch both put total disclosed capital raised at $335M. SI001, SI005
CI031 The public step-up from a $750M seed valuation to a $4B Series A implies about 5.3x valuation growth in under two months. SI002, SI003, SI006
CI032 Public sources identify the Series A as Lightspeed-led with participation from DST Global, NVentures, Radical, Felicis, 49 Palms, Sequoia, and others. SI003, SI024, SI025
CI033 No retained public source discloses Ricursive cash on hand, monthly burn, or runway months. SI001, SI003, SI005
CI034 No retained public source discloses debt facilities, foundry prepayments, or project-finance obligations. SI001, SI003, SI005
CI035 Ricursive appears capital-abundant relative to its visible hiring footprint, but the pace and destination of cash deployment remain opaque. SI001, SI005, SI008
CI036 Public evidence suggests the next financing trigger will be proof of commercial traction or scaled customer adoption rather than mere access to seed capital. SI005, SI006, SI007
CI037 New Scientist says independent experts dispute whether public AlphaChip evidence proves superhuman chip-design performance, creating execution risk for Ricursive's commercial thesis. SI023
CI038 TSMC maintains public annual-report and SEC-filing archives, underscoring how limited Ricursive's private-company financial disclosure is by comparison. SI022
CI039 Crunchbase characterizes Ricursive's $4B Series A as arriving just two months after launch, making financing velocity itself a material diligence issue. SI003, SI004, SI006
CI040 Without pricing, customers, revenue, headcount, board terms, or cash-flow disclosure, this chapter cannot underwrite revenue quality, gross-margin path, or runway from public evidence alone. SI001, SI003, SI005, SI008
CI041 The most supportable financial verdict is that Ricursive has exceptional capital access and a plausible software-scale upside case, but public opacity still blocks full underwriting. SI001, SI005, SI006, SI023
CI042 CompaniesMarketCap shows a last-known $32.90B market cap for Ansys and a June 2026 $41.89B market cap for Autodesk, extending the public comp set into broader engineering-software workflows. SI027, SI031
CI043 CompaniesMarketCap reports TTM revenue of $2.58B for Ansys and $7.20B for Autodesk, showing that specialized design software can scale into multi-billion-dollar revenue without fab ownership. SI028, SI032
CI044 As of June 2026, Arm carries a $406.73B market cap and $4.67B of TTM revenue, illustrating how semiconductor value can accrue to the design/IP layer without owning a foundry. SI029, SI030
CI045 As of June 2026, TSMC carries a $2.198T market cap and $121.91B of TTM revenue, illustrating the scale and capital intensity of the foundry layer that Ricursive does not resemble. SI033, SI034
CE001 Ricursive says it is building self-improving systems that start with chip design. SE001, SE002
CE002 Ricursive says its platform is intended to accelerate and optimize every stage of semiconductor design. SE001, SE002, SE017
CE003 Ricursive describes a recursive loop in which AI designs chips and those chips then enable more capable AI systems. SE001, SE002, SE003
CE004 TechCrunch reported that Ricursive plans to handle everything from component placement through design verification and to use LLMs inside the platform. SE005
CE005 TechCrunch reported that Ricursive targets companies that make electronics and need chips, not just hyperscalers. SE005
CE006 TechCrunch reported that Ricursive is building AI tools that design chips rather than selling chips itself. SE005
CE007 Ricursive’s homepage says the team is behind AlphaChip, RL-CCD, INSTA, and C3PO. SE001
CE008 The Nature AlphaChip paper framed chip floorplanning as a reinforcement-learning problem and reported superior or comparable floorplans in under six hours. SE009, SE010
CE009 Google Research’s circuit_training repository says AlphaChip is open source and reproduces the Nature 2021 methodology with distributed deep reinforcement learning. SE010
CE010 TechCrunch, Lightspeed, and Sequoia each describe AlphaChip-derived methods as having been used across four generations of Google TPUs. SE004, SE006, SE007
CE011 Sequoia and Lightspeed each say AlphaChip compressed floorplanning from months to hours. SE006, SE007
CE012 Lightspeed and Felicis each describe advanced chip programs as taking two to three years and hundreds of millions of dollars, with labor as the main cost driver. SE006, SE008
CE013 Synopsys positions DSO.ai as autonomous RTL-to-GDSII full-flow optimization. SE011
CE014 AWS describes DSO.ai as the industry’s first autonomous AI application for chip design and ties it to AWS ParallelCluster, AWS Batch, and Slurm-style orchestration. SE012
CE015 Cadence positions Cerebrus as an AI-driven chip-design flow that automatically optimizes designs for PPA from RTL to GDS. SE013
CE016 Forbes reported that Cadence’s AI design products have so far concentrated on early optimization stages and design verification rather than end-to-end autonomous chip design. SE014
CE017 Ricursive’s public scope claim is broader than macro-placement alone because public materials explicitly name verification and full-stack iteration across the semiconductor design stack. SE003, SE005, SE017
CE018 No retained public official surface discloses Ricursive pricing, self-serve onboarding, or contract packaging. SE001, SE002, SE003
CE019 No retained public source names a Ricursive production customer or deployment reference. SE001, SE003, SE005, SE017, SE018
CE020 Ricursive’s Ashby board lists seven open roles. SE016
CE021 The open Ricursive roles span EDA algorithms, LLM infrastructure, software infrastructure, design verification, research, and security. SE016
CE022 The public Ricursive jobs board indicates an on-site Palo Alto operating model rather than a broadly distributed engineering team. SE016
CE023 The public INSTA repository says the framework is a GPU-accelerated differentiable static timing analysis engine that achieved 0.999 correlation to a commercial signoff tool and full-graph timing propagation in less than 0.1 seconds on a 15-million-pin design. SE028
CE024 NVIDIA’s INSTA publication page labels the paper as a 2025 DAC Best Paper Award winner. SE031
CE025 NVIDIA’s C3PO publication page labels the work as a 2026 ASP-DAC conference paper on concurrent timing, routability, and wirelength optimization for commercial-quality global placement. SE029
CE026 The Synopsys RL-CCD blog says the DAC 2023 best-paper project applied reinforcement learning to concurrent clock and data optimization and was chosen from more than 1,000 submissions. SE026
CE027 The founder-linked lineage visible in retained sources spans floorplanning, clock-and-data optimization, static timing analysis, and placement-quality optimization rather than a single placement heuristic. SE001, SE026, SE028, SE029
CE028 Because circuit_training is public, sophisticated design teams can inspect and adapt part of the AlphaChip floorplanning methodology without buying a startup product. SE009, SE010
CE029 New Scientist reported that independent experts disputed whether public evidence proved AlphaChip was better than human designers or commercial tools. SE015
CE030 The public moat from macro-placement alone is therefore contestable even if the founders’ technical pedigree is strong. SE010, SE015
CE031 Synopsys and Cadence each already package AI into incumbent design flows, which lowers adoption friction for existing customers relative to a new external platform. SE011, SE012, SE013, SE014
CE032 AWS Trainium is presented as a vertically integrated stack of chip, server, network, software, and orchestration services. SE020
CE033 Google TPU is presented as a managed custom-silicon platform rather than a discrete point component. SE019
CE034 Microsoft’s Maia page benchmarks its accelerator against Trainium and TPU, reflecting how large buyers can solve AI-hardware bottlenecks inside their own stacks. SE021
CE035 These hyperscaler examples raise Ricursive’s deployment bar because some advanced prospects may prefer internal silicon programs or cloud-integrated stacks over adopting a new external design platform. SE019, SE020, SE021
CE036 The Export Administration Regulations cover advanced semiconductors and related technology through licensing controls. SE022, SE023
CE037 BIS’s China-focused controls are designed to restrict China’s ability to produce advanced semiconductors used for military modernization. SE023, SE024
CE038 CSIS and Morrison Foerster both frame export controls around AI chips as a material operating and compliance constraint across the ecosystem. SE024, SE025
CE039 For a platform intended to support semiconductor-design programs, export-control screening and customer-geography policies become practical deployment requirements. SE022, SE023, SE024, SE025
CE040 Retained public Ricursive surfaces do not expose a security center, certification inventory, public status page, or release changelog. SE001, SE002, SE003
CE041 That disclosure gap means enterprise buyers would likely need private proof on PDK handling, data isolation, and signoff workflow trust before deployment. SE011, SE013, SE001
CE042 Converge Digest described Ricursive as aiming to accelerate the full semiconductor design process. SE017
CE043 Semiconductor Digest repeated Ricursive’s claim that it is building a next-generation AI platform for semiconductor design after the seed launch. SE018
CE044 Lightspeed frames Ricursive as a way to democratize custom silicon for companies that do not have massive design teams. SE006
CE045 Sequoia frames the destination state as moving the industry from fabless to designless. SE007
CE046 DSO.ai on AWS and Cadence Cerebrus both market PPA and time-to-market gains rather than a recursive AI-hardware co-design loop. SE012, SE013
CE047 Ricursive’s public differentiation is strongest on recursive AI-hardware co-evolution and full-stack ambition, not on published production benchmarks or customer case studies. SE001, SE003, SE005, SE019
CE048 NVIDIA’s EDA research surfaces and the INSTA repository show that the broader physical-design research environment around the founders now includes public code and publication pages, not just closed papers. SE028, SE030, SE031
CE049 The visible lineage in retained sources runs from the 2021 Nature AlphaChip paper to RL-CCD in 2023, INSTA in 2025, and C3PO in 2026. SE009, SE026, SE031, SE029
CE050 Ricursive’s Series A announcement said the company would use new funding to expand compute infrastructure and iterate faster across the full semiconductor design stack. SE003
CE051 The public INSTA releases page shows no packaged releases, which is consistent with research-tool maturity rather than enterprise product packaging. SE032
CE052 The public circuit_training GitHub surface exposes code and issue tracking but no packaged releases, consistent with a research framework rather than a vendorized product. SE010, SE033, SE034
CE053 NVIDIA’s EDA research lab page shows INSTA and related physical-design publications as part of an active broader research program rather than a single isolated paper. SE030, SE031
CE054 The retained ASP-DAC public award archive fetched in this run does not yet surface a 2026 C3PO entry, so independent award corroboration remains incomplete in the retained bundle. SE027, SE029
CU001 The core Ricursive surfaces reviewed for this chapter do not name a Ricursive production customer or disclose a deployed account. SU001, SU002, SU003, SU004, SU005
CU002 Ricursive publicly positions itself as AI software for semiconductor design rather than as a chip vendor, which implies enterprise design organizations are the intended customers. SU001, SU002, SU004, SU005
CU003 Ricursive’s visible hiring footprint is still engineering-heavy and does not show a scaled public sales or customer-success org. SU009
CU004 Lightspeed says leading-edge silicon programs usually require large teams, two to three years, and hundreds of millions of dollars, which narrows the likely buyer pool to organizations with substantial chip-design budgets. SU006, SU008
CU005 AWS’s Synopsys DSO.ai case study frames AI-assisted chip design as a workflow for complex SoCs, PPA tuning, design reuse, and node migration rather than a consumer-facing product. SU018, SU016
CU006 Cadence markets Cerebrus directly to block engineers and design teams, indicating that physical-design practitioners are the likely day-to-day users of Ricursive-like tools. SU017
CU007 TSMC says it served 534 customers and manufactured 12,682 products in 2025, confirming that advanced silicon development already sits inside a large B2B ecosystem of foundry customers. SU022
CU008 Google Cloud says TPUs are available to external users, so adjacent demand for custom-silicon workflows is not confined to first-party internal Google teams. SU020, SU013
CU009 Microsoft’s Maia 200 launch is another example of workload-specific custom silicon aimed at customer-facing AI inference economics. SU021, SU024
CU010 The likely Ricursive buyer is a compute or silicon program owner, the user is a design or verification team, and the payer is the enterprise funding the silicon roadmap. SU006, SU017, SU018, SU022
CU011 The most plausible Ricursive customer archetypes are frontier AI labs, hyperscalers, large fabless semiconductor companies, and system companies with in-house custom silicon programs. SU006, SU013, SU022, SU024
CU012 DeepMind says AlphaChip has been used across multiple Google TPU generations and was extended by MediaTek, which is the strongest public adjacent proof that the founders have solved a real chip-design workflow for sophisticated users. SU013, SU014
CU013 Sequoia’s podcast says the founders treated the TPU team as their internal customer at Google, showing that their product framing came from a live user workflow rather than pure lab research. SU007
CU014 DeepMind says TPUs are available to external users through Google Cloud, which broadens the practical user surface of the founders’ adjacent AlphaChip work. SU013, SU020
CU015 Ricursive’s launch materials say the company wants to bring its platform to early enterprise, which proves commercialization intent but does not identify any signed account. SU002, SU010
CU016 TechCrunch reported that Ricursive would not name its early customers. SU004
CU017 The same TechCrunch interview said the startup had heard from every big chip-making name and could choose among first development partners, which signals inbound interest but not verified deployment proof. SU004
CU018 Anthropic says it uses over one million Trainium2 chips and that more than 100,000 customers already run Claude on Bedrock, proving that frontier-model labs and their buyers will commit to alternative accelerator platforms at huge scale when economics are strong. SU026, SU027, SU028
CU019 AWS Trainium’s customer page lists Anthropic, Poolside, Decart, Karakuri, AGI House, Hugging Face, Red Hat, and PyTorch, showing adjacent demand from labs, developer ecosystems, and enterprise-software distributors. SU027
CU020 Adjacent custom-silicon customer testimonials emphasize cost, infrastructure availability, throughput, and framework compatibility rather than abstract model novelty. SU027, SU019
CU021 One independent custom-silicon analysis argues that the economics only work once annual inference spend is roughly $500 million or more and workloads are highly uniform. SU024
CU022 The same analysis says hyperscalers were pushed toward custom silicon by cost pressure and by strategic dependence on NVIDIA allocation, roadmap, and pricing. SU024, SU025
CU023 Omdia says foundry expansion, advanced packaging, and HBM supply are structural bottlenecks through at least mid-2027, so design automation alone does not remove deployment friction for end customers. SU025, SU022
CU024 Omdia says foundry customers should lock in 2027 capacity early and secure memory relationships directly, underscoring that downstream customer success depends on supplier orchestration beyond software. SU025
CU025 TSMC says it provides account management, engineering services, online transactions, and an open innovation platform, indicating that chip customers buy into an ecosystem rather than a standalone optimization model. SU022
CU026 Morrison Foerster says export-control enforcement risk extends beyond manufacturers and exporters to the broader AI-chip ecosystem, so customer diligence should include geography and end-use exposure. SU030
CU027 New Scientist recorded expert skepticism about broad “better than humans” AlphaChip claims, which is a reminder not to over-extrapolate founder lineage into current Ricursive commercial proof. SU029, SU013
CU028 Ricursive has not publicly disclosed customer count, deployment count, ARR, NRR, GRR, or renewal data in the sources reviewed for this chapter. SU001, SU002, SU003, SU004
CU029 Because no public contract terms or renewal statistics are disclosed, durability remains unproven rather than negative. SU001, SU003, SU004, SU005
CU030 The public record does not support named logos, NPS, or production-retention claims for Ricursive itself. SU001, SU002, SU003, SU004, SU005
CU031 If Ricursive converts only a small number of reference accounts at first, each one will matter disproportionately because the company has not yet disclosed a diversified installed base. SU001, SU004, SU028
CU032 Ricursive’s commercial motion is likely to be high-touch and partner-heavy because chip-design adoption requires integration with EDA flows, cloud or HPC compute, and foundry processes. SU016, SU017, SU018, SU022
CU033 AWS’s DSO.ai case study says advanced chip-design optimization can require 15 to 30 machines for weeks, so customers will evaluate infrastructure burden along with design quality. SU018
CU034 Cadence customer stories from Broadcom, Imagination, MediaTek, and Renesas show that chip-design-tool buyers expect explicit PPA or productivity proof points before broad adoption. SU017
CU035 Synopsys says DSO.ai optimizes trillions of design recipes across logical and physical domains, so Ricursive is entering a buyer category already saturated with automation claims. SU016, SU018
CU036 Data Center Frontier says Anthropic uses a multi-cloud, multi-accelerator stack across AWS Trainium and Google TPU to preserve supply, pricing, and roadmap resilience. SU028, SU026
CU037 Sophisticated AI buyers appear to prefer optionality rather than single-vendor lock-in, so Ricursive customers may ask for portability across foundry, cloud, and EDA environments. SU028, SU022, SU018
CU038 The strongest supportable public customer proof for Ricursive today is founder lineage plus clear adjacent market demand, not disclosed Ricursive deployment evidence. SU013, SU018, SU026, SU001
CU039 If Ricursive’s first buyers are frontier labs or large silicon teams, the buyer, user, and payer can differ inside one account, which lengthens procurement and validation cycles. SU017, SU018, SU022, SU028
CU040 Anthropic says Claude will be available directly inside AWS with the same account, controls, and billing, which shows that enterprise buyers value procurement rails that fit existing governance. SU026
CU041 AWS Trainium customer references highlight feedback loops with the chip provider and framework teams, suggesting that early Ricursive accounts are likely to demand co-development rather than black-box software sales. SU027
CU042 Trainium customer quotes emphasize lower training cost, higher throughput, and easier access, which are concrete evaluation dimensions a Ricursive reference case would also need to demonstrate. SU027
CU043 Sequoia’s podcast says customers are willing to share data but the founders want it kept private and siloed, implying enterprise confidentiality and data-handling controls will matter in customer diligence. SU007
CR001 Ricursive publicly positions itself as a frontier AI lab building self-improving systems that start with chip design rather than as a chip manufacturer. SR001, SR002
CR002 Ricursive says it has raised $335 million and is scaling a small elite team to pursue AI-driven semiconductor design. SR001, SR002
CR003 Ricursive’s January 2026 Series A was reported at $300 million and a $4 billion valuation less than two months after launch. SR003, SR034, SR035
CR004 TechCrunch reported that Ricursive had raised $335 million total by February 2026. SR003, SR004
CR005 The founding story and most public coverage emphasize Anna Goldie and Azalia Mirhoseini’s AlphaChip pedigree as the core reason investors backed Ricursive. SR003, SR004, SR005, SR006
CR006 Lightspeed describes leading-edge silicon design as a process that can take two to three years and hundreds of millions of dollars. SR005
CR007 Felicis argues traditional EDA tools struggle with accelerator complexity even as the semiconductor market approaches roughly $1 trillion in 2026. SR006
CR008 DeepMind says AlphaChip has generated superhuman or comparable chip layouts in hours and has been used across the last three generations of Google TPUs. SR009, SR008
CR009 DeepMind says AlphaChip has also been adopted by MediaTek and extended across additional stages of the chip-design flow. SR009
CR010 New Scientist reported that independent researchers said Google had not yet proven AlphaChip outperformed expert human designers or commercial software tools on public state-of-the-art benchmarks. SR007
CR011 New Scientist reported criticism that AlphaChip benchmarking was not reproducible and that prior public comparisons to unnamed human designers were easy to game. SR007
CR012 New Scientist reported a critic’s view that reinforcement-learning methods can require two to three orders of magnitude more compute resources than commercial chip-design methods and often trail them in results. SR007
CR013 Cadence markets Cerebrus as a full-flow AI optimization product that improves PPA and productivity and is already used by customers such as Broadcom, Imagination Technologies, MediaTek, and Renesas. SR010
CR014 Synopsys markets DSO.ai as an autonomous RTL-to-GDSII optimization system built around reinforcement learning across trillions of design recipes. SR011
CR015 Forbes reported in February 2026 that Cadence’s AI design products were already part of a multi-year industry shift and that full autonomous chip design was still many years away. SR012
CR016 Cadence’s April 2026 Super Agents launch extended its offering from RTL through analog, physical implementation, and signoff under a common orchestration layer. SR023
CR017 Cadence explicitly warns that general-purpose LLMs operate on probabilistic intuition rather than sound engineering principles unless grounded by EDA-native skills and tools. SR023
CR018 Embedded reported that the dominant EDA vendors are converging on AI-orchestrated but human-supervised workflows rather than full unsupervised autonomy. SR024
CR019 Embedded reported that modern SoC complexity and advanced packaging are increasing engineering hours while a projected shortage of specialized talent widens the execution gap. SR024
CR020 Synopsys said in March 2026 that a large-SoC front-end design and verification process typically takes four to six months using traditional methods. SR025
CR021 Synopsys positioned its 2026 agentic workflow as an incremental productivity improvement of roughly 2x to 5x rather than as proof that verification and signoff are solved. SR025
CR022 Siemens and TSMC said their 2026 collaboration spans automated DRC fixes, digital design acceleration, 3D thermal analysis, and certifications on 3nm, 2nm, A16, and A14 nodes. SR022
CR023 Ricursive’s current public materials and launch press release emphasize founders, papers, and investors but do not name paying customers, disclose revenue, or provide customer case studies. SR001, SR002
CR024 The EAR and BIS AI policy guidance make advanced-semiconductor exports, related technology, and certain model-training activities compliance-sensitive today. SR013, SR014
CR025 BIS’s October 2022 control package was designed to restrict China’s ability to produce advanced semiconductors and remains a foundational constraint on the ecosystem. SR015, SR016
CR026 CSIS argues that allies such as Taiwan, Japan, South Korea, Germany, and the Netherlands control key chokepoints in the AI and semiconductor value chain, limiting the effectiveness of unilateral U.S. policy. SR016
CR027 Morrison Foerster says export-control enforcement now reaches beyond manufacturers and exporters to forwarders, financial institutions, data-center operators, and IaaS providers. SR017, SR024
CR028 Finnegan says the January 2026 AI-chip rule requires exporters to certify U.S. supply, no diversion, a 50% cap on China and Macau shipments, strong KYC, and independent U.S. testing. SR026, SR027
CR029 Mayer Brown says the January 2026 rule also requires applicants to identify remote end users in specified countries of concern and certify that exports will not divert foundry capacity from U.S. users. SR027
CR030 Al Jazeera reported in June 2026 that BIS clarified advanced-AI-chip licensing requirements still apply to China-headquartered firms even when their subsidiaries sit outside China. SR028
CR031 Trade.gov says Taiwan accounts for more than 60% of global foundry revenue and over 90% of leading-edge manufacturing, underscoring concentrated dependence on Taiwan and TSMC. SR030, SR029
CR032 Trade.gov says U.S. semiconductor design firms are key customers of Taiwan’s foundries and that advanced packaging demand remains high with 3nm-and-beyond investment. SR030
CR033 SEMI projected global fab-equipment spending of $110 billion in 2025 and $130 billion in 2026, with roughly 50 new fabs expected to come online across those two years. SR019
CR034 GAO reported that as of July 2025 Commerce had awarded 19 companies for 40 semiconductor projects, but project milestones extend through 2033, so diversification will not arrive on a startup timeline. SR029
CR035 GAO says semiconductor manufacturing remains geographically concentrated in a few regions and that the United States had 0% commercial-scale leading-edge logic share in 2022. SR029
CR036 TSMC’s dedicated foundry site highlights that advanced packaging, mask services, and alliance programs sit inside a specialized external ecosystem that Ricursive would have to rely on rather than own. SR020, SR021
CR037 SEMI’s 2026 U.S. policy priorities say semiconductor manufacturing depends on a global network of specialized materials, equipment, expertise, and workforce programs. SR031
CR038 Semiconductor Digest argues that the dominant foundry model is optimized for scale, expensive mask sets, and long lead times, which can lock startups and low-volume innovators out of domestic manufacturing. SR032
CR039 Oregon State says one state alone expects 6,300 new semiconductor positions and a 24% increase in credentialed workers, illustrating a live sector-wide talent gap. SR033
CR040 Oregon State says dedicated verification training was added after feedback from companies including Apple and Cadence because hardware verification is sought after and insufficiently taught. SR033
CR041 Ricursive’s public job board showed only seven openings, including EDA algorithm, RTL and design verification, LLM infrastructure, research, and a founding security engineer role. SR018
CR042 The combination of a small elite team message and only a handful of specialist openings implies concentration risk across technical, verification, and security functions. SR001, SR018
CR043 Ricursive’s $4 billion valuation is being underwritten publicly on founder pedigree and technical ambition despite the absence of public revenue and customer disclosure. SR001, SR003, SR004, SR023
CR044 Public commercial proof today is dominated by Ricursive, its investors, and adjacent ecosystem voices rather than by named customers, audited metrics, or independent benchmarks. SR001, SR005, SR006, SR023
CR045 The strongest mitigants are exceptional founder-market fit, substantial cash raised early, and the fact that incumbent EDA vendors validate demand for AI-assisted design even while intensifying competition. SR003, SR004, SR010, SR011, SR022, SR025
CV001 Ricursive's January 2026 financing set a high reference price for this chapter's analysis, implying about $13.3 of post-money equity value for every $1 of new primary capital raised. SV001, SV002, SV004, SV005
CV002 Ricursive had previously raised a $35 million seed round at about a $750 million valuation in December 2025. SV003, SV004
CV003 TechCrunch reported that Ricursive had raised $335 million total by February 2026. SV002, SV003
CV004 The January 2026 Series A syndicate included Lightspeed, DST Global, NVentures, Felicis, 49 Palms, Radical Ventures, and Sequoia Capital. SV001, SV004, SV005
CV005 Ricursive was founded by Anna Goldie and Azalia Mirhoseini, whose work on AlphaChip underpins the company’s credibility in AI-driven chip design. SV001, SV003, SV011, SV013
CV006 Ricursive says its platform aims to accelerate semiconductor design and eventually let AI design the silicon substrate for future AI systems. SV001, SV002, SV011
CV007 TechCrunch said AlphaChip could generate high-quality chip layouts in about six hours versus a process that often takes human designers a year or more. SV003
CV008 Ricursive coverage describes AlphaChip-derived methods as learning across designs and extending from placement toward broader design verification tasks. SV003, SV006
CV009 New Scientist reported that independent experts disputed whether AlphaChip had publicly proven superiority over expert human designers or commercial tools. SV019
CV010 New Scientist also quoted a critic who said reinforcement-learning approaches can require orders of magnitude more compute than methods used in commercial chip-design tools. SV019
CV011 Synopsys markets DSO.ai as autonomous RTL-to-GDSII optimization that searches trillions of design recipes to improve performance, power, and area. SV014, SV016
CV012 Cadence markets Cerebrus as an AI-driven chip-design optimizer that can automate multi-block flow exploration and improve PPA and productivity. SV015, SV017
CV013 Forbes reported in February 2026 that Cadence had broadened its AI automation stack with what it called the first AI super-agent for chip design. SV017
CV014 Ricursive therefore enters a market where incumbent EDA vendors already ship AI-assisted automation with customer references and distribution. SV014, SV015, SV016, SV017
CV015 Google TPU, AWS Trainium, and Microsoft Maia sources show hyperscalers continue investing aggressively in custom AI silicon. SV020, SV021, SV022
CV016 BIS, CSIS, and Morrison Foerster sources show export-control and compliance scrutiny remained active across advanced AI and semiconductor ecosystems in 2025-2026. SV031, SV032, SV033, SV034
CV017 That policy backdrop can narrow customer sets or slow commercialization for AI-chip design platforms that operate across sensitive semiconductor programs. SV031, SV033, SV034
CV018 As of June 2026, Synopsys showed about $86.91 billion of market capitalization and about $8.00 billion of TTM revenue. SV023, SV024, SV039
CV019 As of June 2026, Cadence showed about $106.17 billion of market capitalization and about $5.52 billion of TTM revenue. SV025, SV026, SV037
CV020 As of June 2026, NVIDIA showed about $4.969 trillion of market capitalization and about $215.93 billion of TTM revenue. SV027, SV028, SV035, SV038
CV021 As of June 2026, AMD showed about $834.16 billion of market capitalization and about $34.63 billion of TTM revenue. SV029, SV030, SV036
CV022 Those four public references imply simple market-cap-to-revenue proxies of about 10.9x for Synopsys, 19.2x for Cadence, 23.0x for NVIDIA, and 24.1x for AMD. SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV023 Across the four-company set, the simple average market-cap-to-revenue proxy is about 19.3x and the median is about 21.1x. SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV024 None of the cited Ricursive sources publicly disclose current revenue, ARR, gross margin, or customer count. SV001, SV002, SV003, SV011
CV025 The current $4 billion mark is therefore being underwritten mainly on team quality, technical promise, and market narrative rather than on public operating metrics. SV001, SV002, SV003, SV007, SV011
CV026 The jump from a $750 million seed valuation to a $4 billion Series A post-money valuation is about 5.33x. SV003, SV004
CV027 A $300 million primary round at a $4 billion post-money valuation implies a roughly $3.7 billion pre-money valuation and about 7.5% new-money dilution before fees. SV001
CV028 Total disclosed capital raised of $335 million equals about 8.4% of the $4 billion post-money valuation. SV003, SV004
CV029 Lightspeed said Ricursive had already achieved technical progress, but the public materials do not quantify that progress or identify paying customers. SV001, SV007
CV030 Ricursive’s own website emphasizes mission, hiring, and long-horizon compute ambitions rather than current customer deployments. SV011, SV012
CV031 The Ashby jobs page shows Ricursive actively hiring across research and engineering roles, consistent with a buildout phase rather than a mature revenue-scaling phase. SV012
CV032 Expanding the team and compute infrastructure implies meaningful cash burn before monetization is publicly proven. SV001, SV012
CV033 Export-control complexity adds go-to-market friction even if Ricursive sells design tooling rather than finished chips, because customer programs still sit inside controlled semiconductor ecosystems. SV031, SV033, SV034
CV034 The January 2026 Series A can still be rational if Ricursive becomes a strategically important enabling layer for hyperscalers or chip vendors. SV007, SV015, SV020, SV021, SV022
CV035 TechCrunch reported that every big chip-making name had contacted the founders and that Nvidia invested, which supports strategic interest but not booked revenue. SV003
CV036 New Scientist’s technical criticism plus incumbent EDA competition create a credible adverse case that Ricursive’s valuation may be outrunning reproducible commercial advantage. SV014, SV015, SV017, SV019
CV037 A bear case emerges if Ricursive cannot demonstrate customer-relevant speed or PPA gains versus incumbent workflows or cannot convert early partners into repeat paid programs. SV014, SV015, SV019
CV038 A base case assumes Ricursive converts investor enthusiasm into early paid programs but still needs time to prove durable economics, supporting a valuation corridor roughly around the current mark. SV001, SV007, SV015
CV039 A bull case requires measurable design-cycle compression plus compute-efficiency gains on important chip programs, allowing Ricursive to sustain scarcity value above the current mark. SV001, SV007, SV015, SV020, SV021, SV022
CV040 Because the January 2026 round already prices in substantial future success, entry discipline should be milestone-based rather than prestige-based. SV001, SV003, SV019
CV041 TechCrunch and Crunchbase compared Ricursive’s financing context with other frontier-AI startups such as Unconventional AI and Humans&, showing that multibillion-dollar inception valuations were part of the 2025-2026 market backdrop. SV002, SV004
CV042 That frontier-AI peer set shows $4 billion is not unprecedented as a paper valuation, but it does not prove Ricursive can support that mark with future revenue or exit value. SV002, SV004
CV043 If Ricursive eventually traded on a Synopsys-like 10.9x revenue multiple, a $6 billion bull outcome would still require about $550 million of annual revenue. SV023, SV024
CV044 At a $3 billion bear valuation, Ricursive would still need about $155 million of revenue on the 19.3x four-comp average or about $275 million on the Synopsys proxy to justify the mark. SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV045 The most defensible current stance is track / research-more with medium confidence, high risk, and a stretched valuation view. SV001, SV003, SV019, SV023, SV024, SV025, SV026
CV046 Another private round or strategic partnership is easier to support from current evidence than a near-term IPO-style valuation framework. SV018, SV020, SV023, SV024, SV025, SV026
CV047 The gating diligence asks are revenue model, named paying customers, benchmarked performance versus incumbents, gross-margin structure, and the rights embedded in the $300 million Series A. SV001, SV014, SV015
CV048 Public comparables such as NVIDIA, AMD, Cadence, and Synopsys maintain ongoing filing or annual-report disclosure surfaces, highlighting how far Ricursive remains from IPO-grade transparency. SV035, SV036, SV038, SV040, SV041, SV042
来源
编号出版方标题引文
SO001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SO002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence Ricursive Intelligence, a frontier AI lab with the mission to transform semiconductor design, launched today and announced its $35 million seed round led by Sequoia Capital at a $750 million final valuation.
SO003 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design Ricursive Intelligence, a frontier AI lab founded by the co-creators of AlphaChip, today announced a $300 million Series A funding round led by Lightspeed Venture Partners at a $4 billion post-money valuation.
SO004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch Ricursive Intelligence, a startup building an AI system to design and automatically improve AI chips, has raised $300 million at a $4 billion valuation.
SO005 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months Ricursive is building AI tools that design chips, not the chips themselves.
SO006 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SO007 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design Anna Goldie and Azalia Mirhoseini created AlphaChip at Google, using AI to design four generations of TPUs and reducing chip floor planning from months to hours.
SO008 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI Anna and Azalia began exploring ideas together in 2018.
SO009 Ashby Ricursive Intelligence Jobs Open Positions (7)
SO010 Semiconductor Digest Ricursive Intelligence Launches Frontier AI Lab Ricursive Intelligence, an AI lab with the mission to transform semiconductor design, launched today and announced its $35 million seed round led by Sequoia Capital at a $750 million final valuation.
SO011 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design The Palo Alto-based startup was founded by Anna Goldie and Azalia Mirhoseini, the AI researchers behind Google’s AlphaChip system that applied reinforcement learning to chip floorplanning.
SO012 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch Ricursive Intelligence, a frontier AI lab, announced on Monday that it has raised $300 million in a Series A round of funding at a $4 billion valuation just two months after the Palo Alto, California-based company’s launch.
SO013 Nature A graph placement methodology for fast chip design In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics.
SO014 New Scientist Google says its AI designs chips better than humans – experts disagree Independent researchers say the company has not yet proven such AI can outperform expert human chip designers or commercial software tools.
SO015 GitHub google-research/circuit_training AlphaChip is an open-source framework for generating chip floorplans with distributed deep reinforcement learning.
SO016 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area.
SO017 Cadence Cadence Cerebrus Intelligent Chip Explorer Cadence Cerebrus Intelligent Chip Explorer is an AI-driven automated approach to chip design flow optimization that delivers improved PPA and productivity.
SO018 Synopsys DSO.ai: AI-Driven Design Applications By automating the optimization process, Synopsys DSO.ai reduces design time, improves design quality, and helps to unlock the full PPA potential across both logical and physical domains.
SO019 Google Cloud Tensor Processing Units (TPUs) TPUs are custom-designed accelerators purpose-built for AI workloads.
SO020 Microsoft Maia 200: The AI accelerator built for inference Maia 200 is a breakthrough inference accelerator engineered to dramatically improve the economics of AI token generation.
SO021 Amazon Web Services AWS Trainium AWS Trainium is a purpose-built AI chip designed for one goal: the best economics for high performance AI training and inference at scale.
SO022 Bureau of Industry and Security Licensing | Export Administration Regulations Website of the United States Bureau of Industry and Security.
SO023 Bureau of Industry and Security BIS Policy Statement on Controls that May Apply to Advanced Computing Integrated Circuits and Other Commodities Used to Train AI Models BIS has determined that access to advanced computing integrated circuits and other commodities used to train AI models may be subject to an export authorization under the Export Administration Regulations.
SO024 Center for Strategic and International Studies Understanding U.S. Allies’ Current Legal Authority to Implement AI and Semiconductor Export Controls Countries like the Netherlands, Germany, South Korea, Japan, and Taiwan continue to control key chokepoints in the AI and semiconductor value chain.
SO025 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem Enforcement risk extends beyond manufacturers and exporters to include forwarders, financial institutions, and data center operators.
SO026 SEMI Global Fab Equipment Investment Expected to Reach $110 Billion in 2025 Fab equipment spending is projected to rise by 18% in the following year, reaching $130 billion.
SM001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
SM002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SM003 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months
SM004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch
SM005 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SM006 Sequoia Capital How Ricursive Intelligence's Founders are Using AI to Shape The Future of Chip Design
SM007 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SM008 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market
SM009 Cadence Design Systems Cadence Cerebrus Intelligent Chip Explorer
SM010 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design
SM011 Nature A graph placement methodology for fast chip design
SM012 New Scientist Google says its AI designs chips better than humans – experts disagree
SM013 Amazon Web Services AWS Trainium
SM014 Google Cloud Tensor Processing Units (TPUs)
SM015 Microsoft Maia 200: The AI accelerator built for inference - The Official Microsoft Blog
SM016 SEMI Global Fab Equipment Investment Expected to Reach $110 Billion in 2025
SM017 Bureau of Industry and Security Commerce Strengthens Export Controls to Restrict China’s Capability to Produce Advanced Semiconductors for Military Applications
SM018 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem
SM019 CompaniesMarketCap Synopsys (SNPS) - Revenue
SM020 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue
SM021 CompaniesMarketCap Synopsys (SNPS) - Market capitalization
SM022 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization
SM023 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SM024 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI
SM025 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SP001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence Ricursive Intelligence is a frontier AI Lab focused on building self-improving systems, starting with chip design.
SP002 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design AlphaChip was instrumental in establishing AI-driven chip design and has since been adopted across four generations of TPU and deployed by external semiconductor companies.
SP003 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SP004 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months Ricursive is building AI tools that design chips, not the chips themselves.
SP005 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI By automating the optimization process, Synopsys DSO.ai reduces design time, improves design quality, and helps to unlock the full PPA potential across both logical and physical domains.
SP006 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market | Amazon Web Services Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area (PPA).
SP007 Cadence Cadence Cerebrus Intelligent Chip Explorer The Cadence Cerebrus Intelligent Chip Explorer is a transformative, AI-driven, automated approach to chip design flow optimization.
SP008 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design Cadence has now launched the ChipStack AI Super Agent, the world’s first agentic workflow for automating chip design and verification.
SP009 Nature A graph placement methodology for fast chip design A graph placement methodology for fast chip design.
SP010 New Scientist Google says its AI designs chips better than humans – experts disagree Independent researchers say the company has not yet proven such AI can outperform expert human chip designers or commercial software tools.
SP011 Google Research GitHub - google-research/circuit_training AlphaChip is an open-source framework for generating chip floorplans with distributed deep reinforcement learning.
SP012 Google Cloud Tensor Processing Units (TPUs) TPUs are custom-designed accelerators purpose-built for AI workloads and TPUs power Gemini plus Google AI applications serving over 1 Billion users.
SP013 Amazon Web Services AWS Trainium AWS Trainium is a purpose-built AI chip designed for one goal: the best economics for high performance AI training and inference at scale.
SP014 Microsoft Maia 200: The AI accelerator built for inference - The Official Microsoft Blog Maia 200 is the most performant, first-party silicon from any hyperscaler, with three times the FP4 performance of the third generation Amazon Trainium.
SP015 CompaniesMarketCap Synopsys (SNPS) - Market capitalization As of June 2026 Synopsys has a market cap of $86.91 Billion USD.
SP016 CompaniesMarketCap Synopsys (SNPS) - Revenue Revenue in 2026 (TTM): $8.00 Billion USD.
SP017 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization As of June 2026 Cadence Design Systems has a market cap of $106.17 Billion USD.
SP018 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue Revenue in 2026 (TTM): $5.52 Billion USD.
SP019 CompaniesMarketCap NVIDIA (NVDA) - Market capitalization NVIDIA market cap: $4.969 T as of June 2026.
SP020 CompaniesMarketCap NVIDIA (NVDA) - Revenue Revenue in 2026 (TTM): $215.93 Billion USD.
SP021 CompaniesMarketCap AMD (AMD) - Market capitalization AMD market cap: $834.16 Billion as of June 2026.
SP022 CompaniesMarketCap AMD (AMD) - Revenue Revenue in 2025 (TTM): $34.63 Billion USD.
SP023 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch Ricursive Intelligence, a startup building an AI system to design and automatically improve AI chips, has raised $300 million at a $4 billion valuation.
SP024 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence Ricursive Intelligence is building a next-generation platform that uses AI to accelerate and optimize every stage of the semiconductor design process.
SP025 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design Anna Goldie and Azalia Mirhoseini created AlphaChip at Google, using AI to design four generations of TPUs and reducing chip floor planning from months to hours.
SP026 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch Ricursive Intelligence announced it raised $300 million at a $4 billion valuation less than two months after launch.
SP027 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design - Converge Digest Ricursive Intelligence launched a new frontier AI lab focused on accelerating semiconductor design with advanced AI models.
SP028 Semiconductor Digest Ricursive Intelligence Launches Frontier AI Lab - Semiconductor Digest Ricursive Intelligence aims to close the recursive self-improvement loop between AI and the chips that fuel it.
SP029 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform Ricursive Intelligence raised $300 million against a $4 billion valuation for an AI chip design platform.
SP030 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI - SiliconANGLE Ricursive Intelligence nabs $300 million to speed up chip design with AI.
SP031 Synopsys Investor Relations Investor Relations & Investor Resources Synopsys describes itself as a valued partner for global silicon to systems design and lists 35+ years in business, $7+ billion annual revenue, and 28,000+ employees.
SP032 AMD Investor Relations Investors AMD's investor page lists first-quarter 2026 financial results, AI announcements, and more than $10 billion in Taiwan ecosystem investments to accelerate AI infrastructure.
SP033 NVIDIA Investor Relations NVIDIA Corporation - Home NVIDIA's investor home says the company is the world leader in accelerated computing and provides quarterly results, SEC filings, and annual reports.
SI001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SI002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence Ricursive Intelligence, a frontier AI lab with the mission to transform semiconductor design, launched today and announced its $35 million seed round led by Sequoia Capital at a $750 million final valuation.
SI003 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design Ricursive Intelligence, a frontier AI lab founded by the co-creators of AlphaChip, today announced a $300 million Series A funding round led by Lightspeed Venture Partners at a $4 billion post-money valuation.
SI004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch Ricursive Intelligence, a startup building an AI system to design and automatically improve AI chips, has raised $300 million at a $4 billion valuation.
SI005 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months Ricursive is building AI tools that design chips, not the chips themselves.
SI006 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch Ricursive Intelligence, a frontier AI lab, announced on Monday that it has raised $300 million in a Series A round of funding at a $4 billion valuation just two months after the Palo Alto, California-based company’s launch.
SI007 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design. These costs accrue in part to EDA tooling, but the bulk of semiconductor research and development spend goes to labor.
SI008 Ashby Ricursive Intelligence Jobs Open Positions (7)
SI009 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design The company is building a full-stack AI platform to optimize every stage of chip development—layout, optimization, verification, and architecture exploration—creating a continuous feedback loop between model and silicon.
SI010 Synopsys DSO.ai: AI-Driven Design Applications By automating the optimization process, Synopsys DSO.ai reduces design time, improves design quality, and helps to unlock the full PPA potential across both logical and physical domains.
SI011 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market Synopsys DSO.ai searches for optimization targets in very large solution spaces of chip design, utilizing reinforcement learning to enhance power, performance, and area.
SI012 Cadence Cadence Cerebrus Intelligent Chip Explorer Cadence Cerebrus Intelligent Chip Explorer is an AI-driven automated approach to chip design flow optimization that delivers improved PPA and productivity.
SI013 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design The semiconductor industry has been applying AI to accelerate chip design for over three years, achieving 10X productivity gains and focusing primarily on tasks that now seem relatively easy, such as floor-plan optimization using massive recurrent neural networks.
SI014 CompaniesMarketCap Synopsys (SNPS) - Market capitalization As of June 2026 Synopsys has a market cap of $86.91 Billion USD. This makes Synopsys the world's 270th most valuable company by market cap according to our data.
SI015 CompaniesMarketCap Synopsys (SNPS) - Revenue According to Synopsys's latest financial reports the company's current revenue (TTM ) is $8.00 Billion USD. In 2025 the company made a revenue of $8.00 Billion USD an increase over the revenue in the year 2024 that were of $6.07 Billion USD.
SI016 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization As of June 2026 Cadence Design Systems has a market cap of $106.17 Billion USD. This makes Cadence Design Systems the world's 211th most valuable company by market cap according to our data.
SI017 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue In 2025 the company made a revenue of $5.29 Billion USD an increase over the revenue in the year 2024 that were of $4.64 Billion USD.
SI018 CompaniesMarketCap NVIDIA (NVDA) - Market capitalization As of June 2026 NVIDIA has a market cap of $4.969 Trillion USD. This makes NVIDIA the world's most valuable company by market cap according to our data.
SI019 CompaniesMarketCap NVIDIA (NVDA) - Revenue According to NVIDIA's latest financial reports the company's current revenue (TTM ) is $215.93 Billion USD.
SI020 CompaniesMarketCap AMD (AMD) - Market capitalization As of June 2026 AMD has a market cap of $834.16 Billion USD. This makes AMD the world's 19th most valuable company by market cap according to our data.
SI021 CompaniesMarketCap AMD (AMD) - Revenue In 2025 the company made a revenue of $34.63 Billion USD an increase over the revenue in the year 2024 that were of $25.78 Billion USD.
SI022 Taiwan Semiconductor Manufacturing Company Limited Annual Reports - Taiwan Semiconductor Manufacturing Company Limited Annual Reports ... Monthly Revenue ... SEC Filings ... Financial Reports ... 2025 2024 2023 2022 2021 ...
SI023 New Scientist Google says its AI designs chips better than humans – experts disagree Google DeepMind says its artificial intelligence can produce chip designs with “superhuman” performance – but independent experts say public proof is lacking.
SI024 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI The raise comes less than two months after Ricursive was launched by former Google LLC researchers Anna Goldie and Azalia Mirhoseini.
SI025 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform AI chip design company Ricursive Intelligence has raised $300 million in a Series A funding round, resulting in a $4 billion valuation for the company.
SI026 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design Anna Goldie and Azalia Mirhoseini created AlphaChip at Google, using AI to design four generations of TPUs and reducing chip floor planning from months to hours.
SI027 CompaniesMarketCap Ansys (ANSS) - Market capitalization On August 11, 2025 Ansys had a market cap of $32.90 Billion USD.
SI028 CompaniesMarketCap Ansys (ANSS) - Revenue According to Ansys's latest financial reports the company's current revenue (TTM ) is $2.58 Billion USD.
SI029 CompaniesMarketCap Arm Holdings (ARM) - Market capitalization As of June 2026 Arm Holdings has a market cap of $406.73 Billion USD.
SI030 CompaniesMarketCap Arm Holdings (ARM) - Revenue According to Arm Holdings's latest financial reports the company's current revenue (TTM ) is $4.67 Billion USD.
SI031 CompaniesMarketCap Autodesk (ADSK) - Market capitalization As of June 2026 Autodesk has a market cap of $41.89 Billion USD.
SI032 CompaniesMarketCap Autodesk (ADSK) - Revenue According to Autodesk's latest financial reports the company's current revenue (TTM ) is $7.20 Billion USD.
SI033 CompaniesMarketCap TSMC (TSM) - Market capitalization As of June 2026 TSMC has a market cap of $2.198 Trillion USD.
SI034 CompaniesMarketCap TSMC (TSM) - Revenue According to TSMC's latest financial reports the company's current revenue (TTM ) is $121.91 Billion USD.
SE001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
SE002 PR Newswire / Ricursive Intelligence Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SE003 PR Newswire / Ricursive Intelligence Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SE004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch | TechCrunch
SE005 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months | TechCrunch
SE006 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SE007 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SE008 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI
SE009 Nature A graph placement methodology for fast chip design
SE010 GitHub / Google Research GitHub - google-research/circuit_training
SE011 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SE012 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market | Amazon Web Services
SE013 Cadence Cadence Cerebrus Intelligent Chip Explorer
SE014 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design
SE015 New Scientist Google says its AI designs chips better than humans – experts disagree
SE016 Ashby Ricursive Intelligence Jobs
SE017 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design - Converge Digest
SE018 Semiconductor Digest Ricursive Intelligence Launches Frontier AI Lab - Semiconductor Digest
SE019 Google Cloud Tensor Processing Units (TPUs)
SE020 Amazon Web Services AWS Trainium
SE021 Microsoft Maia 200: The AI accelerator built for inference - The Official Microsoft Blog
SE022 Bureau of Industry and Security Licensing | Bureau of Industry and Security
SE023 Bureau of Industry and Security Bureau of Industry and Security
SE024 Center for Strategic and International Studies Understanding U.S. Allies’ Current Legal Authority to Implement AI and Semiconductor Export Controls
SE025 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem | Morrison Foerster
SE026 Synopsys Testing Reinforcement Learning in Chip Design | Synopsys Blog
SE027 ASP-DAC Best Paper|ASP DAC Award Archive
SE028 GitHub / NVlabs GitHub - NVlabs/INSTA
SE029 NVIDIA Electronic Design Automation Research C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization | NVIDIA Electronic Design Automation Research
SE030 NVIDIA Electronic Design Automation Research NVIDIA Electronic Design Automation Research
SE031 NVIDIA Electronic Design Automation Research INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design Applications
SE032 GitHub / NVlabs Releases · NVlabs/INSTA
SE033 GitHub / Google Research Releases · google-research/circuit_training
SE034 GitHub / Google Research Issues · google-research/circuit_training
SU001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Ricursive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SU002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence Ricursive Intelligence will leverage the funding to scale its AI research, expand its compute infrastructure, and bring its platform to early enterprise.
SU003 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design The new funding will be used to scale Ricursive’s world-class research and engineering team and significantly expand its compute infrastructure.
SU004 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months While the young startup won’t name its early customers, the founders say that they’ve heard from every big chip making name you can imagine.
SU005 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch Ricursive is building AI tools that design chips, not the chips themselves.
SU006 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SU007 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design While customers are willing to share data, Anna and Azalia want to keep it private and siloed.
SU008 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI Every frontier model, every hyperscaler, and every new AI-native product ultimately runs into the same constraint: how quickly—and how affordably—we can design the chips underneath it all.
SU009 Ashby Ricursive Intelligence Jobs Open Positions (7)
SU010 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design
SU011 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI
SU012 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SU013 Google DeepMind How AlphaChip transformed computer chip design External organizations are also adopting and building on AlphaChip. For example, MediaTek... extended AlphaChip to accelerate development of their most advanced chips while improving power, performance and chip area.
SU014 Nature A graph placement methodology for fast chip design
SU015 GitHub google-research/circuit_training
SU016 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SU017 Cadence Cadence Cerebrus Intelligent Chip Explorer We use a wide portfolio of Cadence solutions across our business units, and we have seen outstanding PPA improvements from the use of the AI capabilities of Cadence Cerebrus.
SU018 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market This type of AI computation could take 15-30 machines running for weeks at a time... to achieve the PPA targets of a complex chip design.
SU019 Amazon Web Services AWS Trainium
SU020 Google Cloud Tensor Processing Units (TPUs)
SU021 Microsoft Maia 200: The AI accelerator built for inference
SU022 TSMC Dedicated IC Foundry In 2025, TSMC served 534 customers and manufactured 12,682 products.
SU023 Hashrate Index Hyperscaler AI ASIC Market: Google, AWS, Microsoft & More
SU024 Industry Talks Tech The Custom Silicon Arms Race: Why Every Hyperscaler Is Building Its Own Chip The economics only work above ~$500M in annual inference spend with highly uniform workloads and a 5+ year engineering commitment.
SU025 Omdia The $100 Billion Wait: Why Hyperscale Ambitions are Hitting the Foundry Wall Most of the massive capacity intended to save the supply chain won't hit high-volume manufacturing until mid-2027.
SU026 Anthropic Anthropic and Amazon expand collaboration for up to 5 gigawatts of new compute We have worked closely with Amazon since 2023 and over 100,000 customers now run Claude on Amazon Bedrock.
SU027 Amazon Web Services AI Accelerator - AWS Trainium Customers With almost a million Trainium2 chips training and serving Claude today, we’re excited about Trainium3.
SU028 Data Center Frontier Inside Anthropic’s Multi-Cloud AI Factory: How AWS Trainium and Google TPUs Shape Its Next Phase Anthropic is effectively reserving a substantial share of Google’s future TPU capacity and tying that scale directly into Google Cloud’s enterprise AI go-to-market.
SU029 New Scientist Google says its AI designs chips better than humans – experts disagree Google says its AI designs chips better than humans – experts disagree.
SU030 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem Recent actions by the U.S. Department of Commerce’s Bureau of Industry and Security (BIS) and the U.S. Department of Justice (DOJ) highlight how enforcement risk extends beyond manufacturers and exporters to include the broader AI chip ecosystem.
SR001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SR002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SR003 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch Ricursive Intelligence, a startup building an AI system to design and automatically improve AI chips, has raised $300 million at a $4 billion valuation.
SR004 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months
SR005 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SR006 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI Designing leading-edge silicon takes years and hundreds of millions of dollars. Traditional EDA tools struggle to keep up with the complexity of modern accelerators.
SR007 New Scientist Google says its AI designs chips better than humans – experts disagree Independent researchers say the company has not yet proven such AI can outperform expert human chip designers or commercial software tools.
SR008 Nature A graph placement methodology for fast chip design
SR009 Google DeepMind How AlphaChip transformed computer chip design AlphaChip has generated superhuman chip layouts used in every generation of Google’s TPU since its publication in 2020.
SR010 Cadence Cadence Cerebrus Intelligent Chip Explorer Cadence Cerebrus Explorer will intelligently optimize the design to meet these power, performance, and area goals in a completely automated way.
SR011 Synopsys DSO.ai: AI-Driven Design Applications Synopsys DSO.ai reduces design time, improves design quality, and helps to unlock the full PPA potential across both logical and physical domains.
SR012 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design The semiconductor industry has been applying AI to accelerate chip design for over three years, achieving 10X productivity gains.
SR013 Bureau of Industry and Security Licensing | Bureau of Industry and Security
SR014 Bureau of Industry and Security AI Policy Statement on Training AI Models
SR015 Bureau of Industry and Security Commerce Strengthens Export Controls to Restrict China’s Capability to Produce Advanced Semiconductors for Military Applications
SR016 CSIS Understanding U.S. Allies’ Current Legal Authority to Implement AI and Semiconductor Export Controls Countries like the Netherlands, Germany, South Korea, Japan, and Taiwan continue to control key chokepoints in the AI and semiconductor value chain.
SR017 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem Enforcement risk extends beyond manufacturers and exporters to include forwarders, financial institutions, and data center operators.
SR018 Ricursive Intelligence Jobs Ricursive Intelligence Jobs
SR019 SEMI Global Fab Equipment Investment Expected to Reach $110 Billion in 2025 Fab equipment spending is projected to rise by 18% in the following year, reaching $130 billion.
SR020 TSMC Dedicated IC Foundry - Taiwan Semiconductor Manufacturing Company Limited
SR021 TSMC Annual Reports - Taiwan Semiconductor Manufacturing Company Limited
SR022 Siemens Digital Industries Software Siemens & TSMC to advance AI for semiconductor design Siemens is expanding support across the EDA workflow - from automated fixing of design rule violation to certified solutions for leading-edge process technologies.
SR023 Cadence Reimagining Chip Design - From Spec to Signoff with Cadence AI Super Agents General-purpose large language models can generate designs and testbenches, but they operate on probabilistic intuition rather than sound engineering principles.
SR024 Embedded A Look at Agentic AI in the EDA Engineering Workflow The industry’s three dominant players, Cadence Design Systems, Siemens EDA, and Synopsys, are each pursuing ambitious, multi-year plans to develop and deploy agentic AI platforms.
SR025 Synopsys Synopsys Outlines Vision for Engineering the Future This front-end design process typically takes a team of verification engineers four to six months for a large SoC design using traditional methods.
SR026 Finnegan BIS’s New 2026 License Review Process for AI Chips To qualify for a license, companies must certify adequate U.S. supply, no diversion of products, a 50% cap on China/Macau shipments, strict know your customer procedures, and independent U.S. testing.
SR027 Mayer Brown Administration Policies on Advanced AI Chips Codified, with Reverberations Across AI Ecosystem Applicants must certify that exports will not divert global foundry capacity otherwise used for similar or more advanced chips for US end users.
SR028 Al Jazeera US says ban on AI chip shipments applies to Chinese firms outside China The Department of Commerce said its licensing requirements for the export of advanced AI chips applied to all businesses with headquarters or a parent company in China.
SR029 U.S. Government Accountability Office 'GAO-26-107882, SEMICONDUCTORS: Information on Projects Funded to Strengthen U.S. Supply Chain' Manufacturing for certain chip types, such as logic and memory chips, is particularly concentrated in Taiwan and South Korea.
SR030 Trade.gov Taiwan - Semiconductors including chip design for AI Taiwan remains a critical hub in the global semiconductor supply chain, accounting for over 60% of global foundry revenue and more than 90% of leading-edge chip manufacturing.
SR031 SEMI SEMI Outlines 2026 U.S. Policy Priorities to Support Semiconductor Growth, Innovation, and Supply Chain Stability Semiconductor manufacturing relies on a global network of specialized materials, equipment, and expertise.
SR032 Semiconductor Digest 'Innovators Need a Foundry Too: Fixing the U.S. Semiconductor Bottleneck' Today’s dominant foundries are optimized for massive throughput... for many innovators, that model is simply out of reach.
SR033 Oregon State University College of Engineering Solving the semiconductor workforce gap The report estimates the semiconductor sector in Oregon will grow by 6,300 new positions, driving the need for a 24% increase in workers with semiconductor-related credentials.
SR034 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SR035 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SV001 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design Ricursive Intelligence ... announced a $300 million Series A funding round led by Lightspeed Venture Partners at a $4 billion post-money valuation.
SV002 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch
SV003 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months
SV004 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SV005 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SV006 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI
SV007 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SV008 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI
SV009 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SV010 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design
SV011 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI
SV012 Ashby Ricursive Intelligence Jobs
SV013 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SV014 Synopsys DSO.ai: AI-Driven Design Applications
SV015 Cadence Cadence Cerebrus Intelligent Chip Explorer
SV016 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market
SV017 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design
SV018 Nature A graph placement methodology for fast chip design
SV019 New Scientist Google says its AI designs chips better than humans – experts disagree Google DeepMind claims its AlphaChip AI method can deliver “superhuman” chip designs ... but independent experts say public proof is lacking.
SV020 Google Cloud Tensor Processing Units (TPUs)
SV021 Amazon Web Services AWS Trainium
SV022 Microsoft Maia 200: The AI accelerator built for inference
SV023 CompaniesMarketCap Synopsys (SNPS) - Market capitalization
SV024 CompaniesMarketCap Synopsys (SNPS) - Revenue
SV025 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization
SV026 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue
SV027 CompaniesMarketCap NVIDIA (NVDA) - Market capitalization
SV028 CompaniesMarketCap NVIDIA (NVDA) - Revenue
SV029 CompaniesMarketCap AMD (AMD) - Market capitalization
SV030 CompaniesMarketCap AMD (AMD) - Revenue
SV031 Bureau of Industry and Security Commerce strengthens export controls to restrict China’s capability to produce advanced semiconductors used for military applications
SV032 Bureau of Industry and Security AI policy statement on training AI models
SV033 Center for Strategic and International Studies Understanding U.S. Allies’ Current Legal Authority to Implement AI and Semiconductor Export Controls
SV034 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem
SV035 NVIDIA Investor Relations NVIDIA Corporation - Financial Info SEC Filings
SV036 AMD Investor Relations AMD SEC Filings
SV037 Cadence Investor Relations Cadence SEC Filings
SV038 NVIDIA Investor Relations Annual Reports and Proxies
SV039 Synopsys Investor Relations Synopsys Investor Overview
SV040 Synopsys Investor Relations Synopsys SEC Filings
SV041 U.S. Securities and Exchange Commission Cadence Design Systems 2025 Form 10-K XBRL Viewer
SV042 U.S. Securities and Exchange Commission AMD 2025 Form 10-K XBRL Viewer