初创公司尽调
尽调报告 semiconductor EDA / AI chip design automation Series A (private) 2026-07-03

Recursive Intelligence

AlphaChip 谱系在公开商业验证前先遇上 $4B 估值

顶级 AlphaChip 创始人和真实市场瓶颈让 Recursive Intelligence 值得跟踪,但 $4B 入场价已经跑在公开客户和收入证据前面。

封面要素

估值 01
4000 USD M [CO015]
融资总额 02
335 USD M [CO016]
成立时间 03
2025 [CO007]
总部 04
Palo Alto, California, USA [CO005, CO006]

公司概况

Recursive Intelligence 公开使用 Ricursive Intelligence 这一名称,是 Anna Goldie 和 Azalia Mirhoseini 在 Palo Alto 创立的前沿 AI 实验室,目标是自动化并压缩半导体设计周期。公司的叙事是从 fabless 走向 “designless” 定制芯片:客户给出工作负载需求,平台逐步接手架构、物理设计、验证,最终交付制造环节。这一命题有创始人的 AlphaChip 谱系和一线投资人背书,可信度真实存在;但公开证据包仍处早期——技术野心和融资证明很强,收入披露、客户牵引和运营控制偏弱。

官网
www.ricursive.com
成立时间
2025-01-01
创始人
Anna Goldie, Azalia Mirhoseini
创立地点
Palo Alto, California, USA
总部
Palo Alto, California, USA
产品
AI 驱动的芯片设计软件和服务,意在从单阶段设计加速走向从工作负载到 GDSII 的半导体自动化。
客户
超大规模云厂商、前沿模型实验室、半导体公司,以及其他希望获得定制芯片、但不想自建完整芯片设计组织的工作负载拥有方。
商业模式
企业软件加高触达设计项目,未来围绕 AI 驱动的设计自动化做平台化。
阶段
Series A (private)
融资情况
2025 年 12 月发布时获得 $35M 种子轮,随后于 2026 年 1 月以 $4B 估值完成 $300M Series A,已披露融资总额为 $335M。
[CO001, CO004, CO005, CO007, CO008, CO009, CO010, CO015]

执行摘要

主要优势

  • 来自 AlphaChip 及多项后续芯片设计研究项目团队,founder-market fit 罕见。
  • 市场问题巨大且具战略重要性:芯片设计仍慢、贵,并受人才约束。
  • 对仍处商业化早期的公司而言,资本基础和投资人组合异常强。

主要风险

  • 目前没有公开收入、ARR、毛利率或具名付费客户证据支撑 $4B 估值。
  • Synopsys、Cadence、Siemens 等既有厂商已经把 AI-assisted EDA 交付到生产客户工作流。
  • 面向敏感客户设计数据的信任、隐私、安全和质量控制披露仍很薄。
  • Series A 的股权结构经济性、治理权和下行保护条款未披露。

未决问题

  • Recursive、Ricursive 和官网 typo 等变体之间的确切法律名称、注册记录和最终品牌口径。
  • Ricursive 设计输出的具名客户部署、tape-outs 和 post-silicon benchmark 结果。
  • 收入模型、定价、毛利率、烧钱速度、现金跑道和下一轮触发指标。
  • 董事会构成、清算优先权以及制造 / signoff 合作伙伴细节。

目录

Chapter 01

01公司概览

1.1 身份、命名与当前定位

第一项尽调问题是身份卫生。本次任务请求的公司名是 Recursive Intelligence,但公开语料持续使用 Ricursive Intelligence;官网首页标题又多出一个拼写错误,把品牌写成 Riculsive Intelligence。TechCrunch 也提醒读者不要把 Ricursive 与 Richard Socher 那家名称相近的创业公司 Recursive 混淆,因此别名风险不是表面瑕疵。撇开这一点,运营叙事是一致的:Ricursive 把自己定位成一家用 AI 加速半导体设计的前沿 AI 实验室,TechCrunch 2 月的特写也明确称,公司卖的是设计芯片的软件,而不是自己造芯片。独立报道把公司放在 Palo Alto;当前阶段更适合描述为私营、Series A 后,而不是隐身或仅停留在概念。后续章节的核心判断是:命名层存在身份混乱,但产品命题、创始人和融资路径都指向同一家公司。[CO001, CO002, CO003, CO004, CO005, CO006]

KPI 快照表
指标数值 / 状态日期置信度缺口
公开运营名称Ricursive Intelligence2026-07-03本次任务请求使用 Recursive Intelligence,官网标题又将名称误拼为 Riculsive,因此仍需核验法定名称
总部Palo Alto, California2026-07-03公开证据来自招聘和独立报道,而不是官网披露的邮寄地址
启动 / 创立里程碑启动时 $35M 种子轮2025-12-02已审阅公开来源未显示确切注册日期和法人实体文件
当前阶段私营,Series A 后2026-07-03没有公开备案或官方董事会材料说明 Series A 后的治理安排
核心产品面向半导体设计的 AI 软件平台2026-02-16公开材料讲清了论点,但没有披露详细 SKU、定价或部署模式
最新有证据支持估值$4B 投后2026-01-26Series A 估值有证据支持,但已审阅来源未公开披露后续估值标记
累计融资$335M2026-02-16股权表持股、清算优先权和二级交易未披露
公开收入 / ARR2026-07-03已审阅来源未披露收入或 ARR
公开客户数2026-07-03公开材料讨论了目标客户,但没有公开具名客户数量或参考客户名单
公开员工数2026-07-03只有招聘证据公开;总员工数仍未披露
招聘足迹7 个 Palo Alto 现场全职职位2026-07-03开放岗位是扩张信号,不能替代实际员工数
董事会披露未公开披露2026-07-03已审阅来源未发布董事席位、观察员或独立董事信息

混合了证据充分的融资和地点事实,以及对无支撑商业指标和治理细节的明确空值。

[CO001, CO005, CO007, CO008, CO015, CO016]
FO002: 公司快照逻辑

Ricursive 当前故事把创始人履历接到 AI 芯片设计软件,再把资本转成 Palo Alto 招聘;但收入、客户和治理缺口未解,仍限制投资测算信心。

[CO001, CO003, CO004, CO012, CO015, CO016]

1.2 创始人、技术履历与治理可见度

创始人与市场匹配度是公开记录里最清楚的优势。Anna Goldie 和 Azalia Mirhoseini 多次被列为 Ricursive 联合创始人,Goldie 任 CEO,Mirhoseini 任 CTO;TechCrunch 2 月更深入的访谈把两人描述为长期合作者,路径从 Google Brain、Anthropic、再回到 Google,最终同步走到 Ricursive。可信度不只是简历。Sequoia、TechCrunch 和 Google DeepMind 都把二人与 AlphaChip 连接起来,DeepMind 2024 年的文章提供了外部证据:Ricursive 出现之前,这项工作已经有分量。话虽如此,公开治理披露仍然很浅。已审阅资料清楚列出投资人并引用合伙人观点,但没有发布董事会名单、独立董事或具体控制权。结果是一种典型前沿实验室格局:技术领导力和外部验证一开始就异常强,但正式治理、继任深度,以及公司商业叙事在多大程度上仍集中于两位创始人,仍是实质性尽调缺口。[CO009, CO010, CO011, CO012, CO013, CO014]

管理层与创始人表
领导者 / 治理事项当前角色 / 状态背景或公开证据重要性依赖 / 缺口
Anna Goldie联合创始人兼 CEOTechCrunch 和发布稿公开确认;此前任职于 Google Brain 和 Anthropic主要商业叙事者,也是 AlphaChip 创始组合的一员关键人依赖高
Azalia Mirhoseini联合创始人兼 CTOTechCrunch 和发布稿公开确认;共同创造 AlphaChip,加入 Ricursive 前曾在 Stanford 任教主导技术架构和芯片设计自动化论点关键人依赖高
公开技术班底仅按类别披露官网和 Series A 公告称团队人才来自 Google DeepMind、Anthropic、NVIDIA、Cadence、Apple、xAI、 Stanford、MIT 和 Harvard显示公司正在创始人之外,向半导体、系统和模型领域招聘创始人以下具名高管大多未披露
治理 / 董事会披露未公开具名已审阅的公司、投资方和媒体来源披露了投资人,但未披露董事或观察员权利估值这么早达到 $4B,董事会设计会很关键正式治理仍是重大尽调缺口
职能覆盖建设研究、EDA、基础设施、RTL 和安全招聘可见Ashby 岗位显示公司正在为验证、基础设施、安全和模型研究配备人员说明 Ricursive 在搭建运营公司,而不只是创始人实验室财务、销售或法务负责人名单仍未披露

公开证据有力支撑创始人组合和技术班底叙事,但不支撑正式董事会构成或完整高管名单。

[CO009, CO010, CO011, CO012, CO013, CO024]

1.3 融资形成、利益相关方地图与缺失的运营指标

Ricursive 的融资节奏异常快;在核心数字上,融资记录也比运营指标更有交叉印证。公司公告和独立报道一致显示,这家创业公司于 2025 年 12 月发布时获得 Sequoia 领投的 $35M 种子轮,随后在 2026 年 1 月 26 日以 $4B 估值完成 Lightspeed 领投的 $300M Series A,已披露资本合计 $335M。公开投资人组合也有战略意义:Sequoia 做种子轮,Lightspeed 领投下一轮,NVentures 加入,DST、Felicis、Radical 和 49 Palms 都出现在官方公告里。缺失的信息同样重要。同一组资料没有披露收入、ARR、客户数或总员工数,部分二级报道甚至把轮次表述弄错。因此,投资人可以高度相信融资时间线,但对当前经营规模只能给低到中等信心;公开事实只说明公司在招聘和基础设施上投入,而不是发布牵引指标。[CO015, CO016, CO017, CO018, CO019, CO020]

利益相关方与投资方图谱
利益相关方角色公开关联重要性尽调要求
Sequoia Capital种子轮领投方和公开放大器领投 $35M 启动轮,并主持 2026 年 1 月创始人播客最早的蓝筹背书方,也持续向其他投资人释放信号确认 Series A 后持股、董事会权利和按比例跟投权
Lightspeed Venture PartnersSeries A 领投方以 $4B 估值领投 $300M Series A,并发布投资论点当前估值标记下最可见的新资金领投方索取领投方条款和治理权利
NVentures / NVIDIA战略投资方出现在官方 Series A 参与方名单将 Ricursive 连接到占主导地位的 AI 计算生态和潜在芯片设计需求区分投资信号和任何实际商业合作
DST Global财务投资方出现在官方 Series A 参与方名单为银团增加后期成长资本信号澄清持股比例和后续跟投意愿
Felicis VenturesSeries A 参与方出现在官方 Series A 参与方名单将风险资本支持拓展到半导体专业叙事之外确认持仓规模和任何治理权利
Radical VenturesSeries A 参与方出现在官方 Series A 参与方名单显示围绕创始论点的专业 AI 信念澄清支持是战略性、招聘导向,还是纯财务性
49 Palms VenturesSeries A 参与方出现在官方 Series A 参与方名单在 $4B 估值下为银团补足额外资本支持索取确切出资规模和经济条款

本表记录具名利益相关方,不代表完整资本结构表;经济权利和控制条款仍未披露。

[CO015, CO017, CO018, CO019, CO022, CO038]
FO003: 快照 KPI

公开支撑的 KPI 中,融资和招聘最强;收入、客户和治理披露仍是概览的主要限制。

[CO015, CO016, CO026, CO031, CO032, CO038]

1.4 里程碑、招聘信号与反向背景

里程碑记录显示,公司正从研究履历迅速转向资本化建设,但还没走到公开商业验证。公司成立前的可信度来自 AlphaChip 工作;随后 Ricursive 于 2025 年 12 月公开发布,通过 Sequoia 2026 年 1 月播客拓宽命题,并几乎立刻在 Palo Alto 集中发布 EDA、基础设施、验证、安全和研究岗位。这组招聘组合重要,因为它指向一个全栈芯片设计软件工程,而不是狭窄实验室项目。TechCrunch 2 月报道进一步收窄市场切口:Nvidia 既是投资人,Nvidia、AMD、Intel 及其他芯片制造商也是目标客户。反向面也真实存在。CIOL 的怀疑式表述和其他噪声较大的二级报道显示,$4B 估值更多押在创始人履历和基础设施重要性上,而不是已披露收入或可公开引用的客户背书。公开搜索也没有找到具名监管事件或商业合作,因此这些领域仍是明示尽调缺口,而非已经清掉的检查点。[CO021, CO022, CO025, CO026, CO027, CO028]

里程碑表
日期事件类型金额 / 估值 / 状态参与方含义
2024-09-26DeepMind 发布 Anna Goldie 和 Azalia Mirhoseini 撰写的 AlphaChip 影响力文章产品公司成立前的技术证明Google DeepMind;创始人说明核心芯片设计论点早于 Ricursive 本身
2025-12-02Ricursive 启动并宣布种子轮融资创立$35M,估值 $750MRicursive;Sequoia Capital公司公开亮相,并形成第一个估值锚
2026-01-14Sequoia 播客详述“designless”定制硅论点治理公开战略框架参与方:Sequoia、Anna Goldie、Azalia Mirhoseini让产品愿景超越泛泛的 AI 基础设施叙事,更加清晰
2026-01-19Ashby 招聘板显示 7 个 Palo Alto 现场岗位,覆盖工程、研究、安全和通用招聘扩张7 个开放岗位Ricursive显示启动后团队快速搭建
2026-01-26Lightspeed 领投的 Series A 完成融资$300M,$4B 投后估值投资方:Lightspeed、DST、NVentures、Felicis、49 Palms、Radical、Sequoia确认从种子轮到独角兽估值的跃升异常迅速
2026-01-28质疑性报道提出估值是否跑在商业证据前面负面未引用公开的已流片芯片证据CIOL 和二级媒体说明融资速度本身就是风险叙事的一部分
2026-02-05公开招聘板出现 EDA Algorithm Engineer 岗位扩张芯片设计自动化招聘Ricursive显示公司直接向 EDA 工作流深水区配备人员
2026-02-16TechCrunch 刊发创始人画像,并报道累计融资 $335M产品累计融资 $335M来源:TechCrunch、Anna Goldie、Azalia Mirhoseini把估值与创始人履历连接起来,并指出芯片制造商是目标客户
2026-02-27SWE Infrastructure 招聘继续扩张基础设施岗位开放Ricursive说明研发原型之外还有内部工具和系统投入
2026-03-18RTL 和设计验证工程师岗位出现扩张验证岗位开放Ricursive强化了全栈芯片设计工具建设,而不只是模型实验

日期使用发布或岗位发布日期,因为内部决策日期和私有客户里程碑未公开披露;监管和合作伙伴里程碑仍是证据缺口。

[CO007, CO013, CO015, CO016, CO026, CO027]
FO001: 公司里程碑时间线

公开里程碑显示,Ricursive 从公司成立前的 AlphaChip 背书,快速跳到上线、独角兽融资和 Palo Alto 集中招聘;商业指标出现前,质疑已经出现。

由于内部日期和客户部署日期未披露,使用发布日期和招聘发布日期作为公开里程碑锚点。

[CO007, CO012, CO013, CO014, CO015, CO022]

1.5 展示材料

Chapter 02

02市场分析

2.1 市场边界、纳入支出与替代品

Recursive Intelligence 公开品牌为 Ricursive Intelligence,应按 AI 芯片设计自动化平台分析,而不是半导体制造商、晶圆代工厂、晶圆厂设备供应商或 AI 芯片卖方。公司官网、发布材料和独立报道都把它放在软件层:帮助工程师更快做出定制芯片。这一区分重要,因为前沿 AI 投资很容易借用 AI 加速器收入、晶圆代工收入或晶圆厂设备资本开支等巨大相邻数字,然后称之为 TAM。这些资金池是需求驱动因素或背景,不是 Ricursive 实际售卖进入的市场。 最应纳入的支出,是能改善芯片设计工作流的软件和服务:布局规划、PPA 优化、设计收敛、验证辅助,以及在公司证明能够超出布局之后,最终进入架构探索。现状替代方案仍是劳动密集型的传统 EDA 流程,工程团队在既有工具里手工迭代,直到设计收敛。最近的相邻替代品,是 Synopsys 和 Cadence 已经出售的 AI 模块。这些既有厂商证明类别存在,但也收窄边界:Ricursive 可信的市场是芯片设计内部的自动化层,不是整个半导体价值链。[CM001, CM002, CM003, CM004, CM005, CM006]

市场定义表
细分 / 类别纳入支出排除支出买方 / 付费方意义
广义 EDA 和 IP 软件池仅借既有厂商收入作为软件上限晶圆代工服务、掩模、制造、晶圆厂设备半导体设计组织的 CAD / 硅工程预算最有意义的广义背景,因为 Ricursive 卖进的是软件工作流,而不是硬件资本开支
AI PPA / 布局规划自动化布局、PPA 搜索和流程优化模块的点工具支出与芯片设计无关的通用 ML 工具物理设计和 CAD 团队直接切中 Ricursive,因为今天公开的既有厂商证据在这里最强
全栈 AI 芯片设计自动化从布局延伸到验证、设计收敛和更广平台编排的工作流自动化成品芯片、晶圆产出、代工产能硅平台和工程负责人这是 Ricursive 的核心论点;如果证据成立,也是它可能捕获的最大软件层
定制硅项目设计预算附着在战略 ASIC 或加速器项目上的自动化叠加层和增量软件 / 服务支出流片制造成本和云推理收入超大规模云厂商、fabless 或 OEM 芯片项目负责人定义了近期最可能服务的市场,速度 ROI 在这里最高
晶圆厂设备和代工资本开支None晶圆厂工具、工艺设备、封装线、代工收入半导体制造商和晶圆代工厂重要需求背景,但不是 Ricursive TAM
AI 加速器销售和云 AI 收入NoneGPU、TPU、Trainium、Maia、云服务收入云和平台业务单元这是下游需求信号,不是 Ricursive 开票的软件市场

边界纪律在这里很重要:纳入支出仅限于芯片设计软件和相邻自动化服务。来自 AI 加速器、晶圆厂设备或代工厂的大硬件数字被明确排除在 Ricursive TAM 之外,尽管它们会增强定制硅项目的紧迫性。

[CM001, CM004, CM015, CM021, CM029, CM030]
FM001: 市场规模测算视角

三层规模测算栈:从既有设计软件的宽口径天花板,到 Ricursive 的近期滩头阵地。

中层和底层是分析师估计,锚定在可观察的 Synopsys 加 Cadence 收入天花板之下;明确不来自晶圆厂设备或 AI 芯片收入池。

[CM022, CM024, CM027, CM039]

2.2 多重测算视角与相互矛盾的估计

最好的市场规模纪律,是先看一个宽口径、可观察的天花板,再逐步向下收。EDA 和 IP 软件大盘最干净的上限代理,是既有厂商收入:CompaniesMarketCap 报告 Synopsys 2025 年收入约 80.0 亿美元、Cadence 约 52.9 亿美元,合计约 132.9 亿美元;2026 年滚动十二个月口径也接近 135.2 亿美元。这个视角仍不完美,因为这些收入包括 Ricursive 尚未替代的传统流程、IP 和企业关系。但相比借用半导体资本开支或 AI 芯片收入,它更站得住。 第二个视角是下游紧迫性。SEMI 预测 2025 年晶圆厂设备支出为 1100 亿美元、2026 年为 1300 亿美元,说明 AI 相关芯片需求正把资本形成推过硬件栈。但它不会一比一转化成 Ricursive 的软件 TAM。需要保留的矛盾是:围绕定制芯片的风投叙事,在紧迫性方向上是对的;但当前已经货币化的软件控制点,远小于相邻硬件资金池。因此,这里的窄口径市场估计采用低 / 基准 / 高区间,并锚定既有厂商软件天花板,而不是总半导体支出。[CM020, CM021, CM022, CM023, CM024, CM025]

TAM / SAM / SOM 规模测算口径表
发布方 / 口径年份地域数值CAGR / 增长方法置信度局限
CompaniesMarketCap / Synopsys 收入2025全球USD 8.00B较 2024 年同比 31.9%用可观察的既有厂商收入,代理广义 EDA/IP 软件需求包含传统软件和 IP,不只是 AI 自动化
CompaniesMarketCap / Cadence 收入2025全球USD 5.29B较 2024 年同比 14.1%用可观察的既有厂商收入,代理广义 EDA/IP 软件需求包含传统软件和服务,不只是 AI 自动化
分析师综合 / 广义软件上限2025-2026全球USD 13.29B-13.52B低双位数增长汇总 Synopsys 和 Cadence 收入;作为广义设计软件控制点的外层上限仍宽于 Ricursive 可能服务的市场,也不是直接的 Ricursive TAM
SEMI / 晶圆厂设备背景2025全球USD 110B同比 +2%World Fab Forecast 对前道晶圆厂设备支出的预测相邻硬件资本开支,不是软件 TAM
SEMI / 晶圆厂设备背景2026 年预测全球USD 130B同比 +18%前瞻资本开支信号,显示 AI/HPC 驱动的硬件栈紧迫性仅可作为需求驱动因素,不能视为 Ricursive 收入池
分析师综合 / 狭义 AI 自动化 SAM2026 年当前状态全球USD 2.0B-5.0Bn/a假设广义 EDA 支出中只有一部分会迁移到最先进定制硅项目的多阶段 AI 自动化需要在公开布图规划 / PPA 证据之外,证明扩展能力
分析师综合判断 / 近期滩头 SOM2026 年当前状态全球USD 0.5B-1.5Bn/a假设早期获取集中在区块级和点工具式自动化,服务痛点最高的设计团队取决于信任、试点转化和预算归属;这些目前尚未公开

本表有意采用多重口径。宽口径天花板来自现有厂商软件收入;较窄的 SAM 和滩头 SOM 是分析师估算,明确低于该天花板,也避免把半导体资本开支当成软件 TAM。

[CM020, CM021, CM022, CM023, CM025, CM026]
FM002: 市场估计区间

AI 芯片设计自动化三种范围的低 / 基准 / 高年度支出区间,均以 USD billions 计。

低 / 基准 / 高数值均为年度软件支出估计,单位为 USD billions。第一行假设 AI 仍保持窄口径、以点工具为主;第二行假设先进定制硅团队更广泛采用多阶段自动化;第三行使用 2024-2026 Synopsys 加 Cadence 收入作为外层天花板,而不是现实的近期 SAM。

[CM023, CM026, CM027, CM028]

2.3 买方分层、预算归属与采用路径

公开证据表明,Ricursive 最早的买方不是所有地方的所有芯片用户,而是日程压缩价值数百万美元、且定制芯片已经具备战略意义的组织。TechCrunch 称任何制造电子产品且需要芯片的公司都在范围内,但现实中的第一波更窄:超大规模云厂商的硅团队、先进制程 fabless 芯片设计商,以及构建定制 ASIC 的系统公司。这些买方已经长期承受漫长设计周期、高昂工程团队成本,并面临越来越大的压力,要靠定制芯片做差异化。 使用者比买方集合更具体。物理设计、CAD 和验证团队会先评估产品,因为 Synopsys 和 Cadence 的既有案例仍扎根于 PPA 和流程优化。预算权力很可能从这些团队起步;一旦工具触及多个工作流阶段或企业级算力承诺,再向上扩展。因此,采用路径应被理解为分阶段信任曲线:先建立基准可信度,再在单个模块上试点,随后延伸到验证或签核,最后才进入项目级标准化。这一顺序会让 Ricursive 的近期 SOM 小于其标题叙事。[CM003, CM005, CM006, CM007, CM015, CM031]

细分市场 / 买方地图
细分市场买方用户付款方工作流预算负责人采用触发因素
超大规模云厂商硅团队硅负责人或平台工程负责人物理设计、CAD 和验证工程师硅项目 / 基础设施工程预算面向内部云工作负载的定制 AI 加速器硅或工程 VP(可能)需要缩短战略性第一方 AI 硅的开发周期
无晶圆厂先进制程芯片公司设计平台负责人或物理设计总监模块负责人、实现团队、验证负责人中央 EDA / R&D 预算CPU、GPU、网络或加速器 SoC 收敛CAD / 设计平台高管昂贵设计面临 PPA 压力和反复收敛循环
构建定制 ASIC 的系统 / 电子公司SoC 项目负责人或产品工程负责人较小的内部芯片设计团队加外部服务事业部工程预算面向差异化设备或子系统的定制 ASIC产品或工程 GM需要在不把路线图拉长数年的情况下,把更多硅差异化能力内化
设计服务 / IP 集成伙伴服务线负责人或方法学负责人实现工程师项目利润 / 服务预算设计迁移、实现和重用占比较高的流程业务实践或交付负责人需要压缩迭代时间,并提升客户项目之间的复用
正在扩展范围的现有 EDA 点工具用户企业 CAD 或方法学负责人已使用布局 / PPA 工具的现有模块团队企业软件预算从点状自动化扩展到更广的工作流标准化中央 EDA 治理小组证明自动化能从单个模块延伸为组织范围内可重复的工作流收益

预算负责人标签部分根据公开资料中成熟工具的描述推断;确切审批路径仍是尽调缺口, 不能被夸大成既定事实。

[CM015, CM031, CM032, CM033, CM035, CM040]
FM003: 买方 / 细分市场地图

Ricursive 最可能早期细分市场中的买方 - 用户 - 付款方关系和就绪度。

就绪度和匹配度只是序数判断,依据公开工作流描述和买方痛点信号;不是基于 Ricursive 披露的胜率或客户背书。

[CM003, CM015, CM031, CM032]
FM004: 采用漏斗或价值链图

由证明牵引的采用路径:从基准可信度走向企业工作流标准化。

该漏斗是一个机制模型,综合了在位 AI-EDA 工具的公开描述,以及独立质疑基准证明时暴露出的信任顾虑。

[CM032, CM035, CM036, CM040]

2.4 增长驱动、采用约束与估值关联

需求侧是真实的。超大规模云厂商已经大规模运营第一方芯片项目:AWS 推广 Trainium 用于 AI 训练和推理,Google 称 TPU 支撑 Gemini 和更广泛的 AI 技术栈,Microsoft 称 Maia 200 改善自有集群内的推理经济性。再叠加 Lightspeed 的观点——顶级芯片项目仍要消耗数年和数亿美元——增长驱动逻辑很强。Ricursive 不需要全世界每一家半导体公司都购买平台才能重要;它只需要在时间和人才最稀缺的定制芯片项目中拿到有意义的份额。 约束侧同样重要。公开证明在布局规划和 PPA 优化上最强;延伸到验证和全栈自动化的更宽主张,还没有具名设计胜利或公开基准来支撑。New Scientist 对 AlphaChip 公开证据的怀疑很重要,因为关键任务设计软件买方对可复现性、保密性和切换成本异常敏感。出口管制又加了一层摩擦,影响哪些客户、晶圆厂和伙伴能够被干净服务。对估值而言,这意味着应按证明里程碑和企业采用证据来承销 Ricursive,而不是只看宽泛 TAM 话术。[CM010, CM011, CM012, CM013, CM014, CM016]

增长驱动因素和约束表
驱动因素 / 约束方向时点含义尽调要求
超大规模云厂商定制硅竞赛正向现在至 2028 年以后持续推高买方对更快设计周期的紧迫感,也提高他们在战略项目上测试自动化的意愿梳理正在推进的第一方硅路线图,以及哪些环节的进度压缩最有价值
老牌厂商 AI-EDA 证明点正向现在让 AI 辅助设计采购变得常规,也让工程团队内部更容易解释 Ricursive用老牌厂商案例对标 Ricursive 的试点主张
布图规划和 PPA 痛点正向持续漫长设计周期和手工收敛循环,构成高价值问题量化每个先进项目的人力、算力和进度成本
从布局扩展到验证若获证明则正向2026-2028从点工具转向平台预算,会显著扩大 Ricursive 的 SAM要求提供公开或客户背书的证据,证明验证主张能在实践中跑通
切入根深蒂固 EDA 栈的切换成本负向持续即便点性能更强,如果集成和方法学风险过高,也可能无法转化在试点中测试迁移工作量、工作流互操作性和回滚选项
窄任务之外的公开证据缺口负向现在缺少具名胜利、定价和验证基准,使商业信任低于高调叙事索取基准测试包、客户背书和可重复性证据
出口管制和执法风险负向现在至 2026 年以后可能限制先进制程项目中的客户组合、代工关系或伙伴工作流审查目标账户对 BIS 管制的暴露,以及任何代工厂或云合作伙伴限制
晶圆厂设备和 AI 需求热潮正向但间接2025-2026支撑定制硅的战略价值,但不直接决定 Ricursive TAM把硬件背景数字与软件市场规模主张分开

驱动因素表区分采用力量与市场规模分母。庞大的硬件需求数字能解释紧迫性,但 Ricursive 仍需证明工作流信任,才能把这些力量转化为软件预算获取。

[CM010, CM012, CM013, CM014, CM019, CM020]

2.5 展示材料

Chapter 03

03竞争对手

3.1 格局横跨直接既有厂商、相邻领域、替代路径和资本支持的新进入者

Recursive Intelligence 公开品牌为 Ricursive Intelligence,它进入的不是空白类别。最清楚的直接商业替代,是 Synopsys DSO.ai 和 Cadence Cerebrus;Cadence 2026 年的 ChipStack AI Super Agent 又把这种竞争从后端优化延伸到前端设计和验证。Siemens Solido 通过营销 AI 支持的变异感知设计、IP 验证、表征和仿真,把既有厂商阵地扩展到相邻的定制 IC 工作流。这三组既有产品族比多数早期创业公司更重要,因为它们已经嵌在半导体组织内部,而这些组织信任它们的支持模式、签核流程和采购动作。 替代品集合同样重要。AlphaChip 和开源 circuit_training 仓库,让强化学习布局规划谱系的一部分可以被顶尖内部团队复现。Google、AWS 和 Microsoft 都公开描述了第一方 AI 加速器,这意味着最先进的买方可以通过内部芯片项目应对硬件瓶颈,而不是采用外部自动化创业公司。更简单的替代品是商用硬件:NVIDIA 和 AMD 让买方通过采购解决近期 AI 算力需求,而不是启动多年定制芯片项目。 潜在新进入者再加一层压力。Cognichip 明确试图把深度学习用于芯片设计;MatX 和 Rebellions 则说明,相邻芯片创业公司可以把资本、人才和买方注意力拉向硬件主导的替代方案。因此,实际竞争地图不只是 Recursive 对另一家年轻创业公司;而是 Recursive 对根深蒂固的 EDA 既有厂商、开源或内部自建路径,以及资本密集型硬件选项——这些选项会让许多买方不再需要定制设计。[CP001, CP002, CP004, CP005, CP008, CP009]

竞争格局表
替代类型代表选项为什么竞争同一任务成熟度或限制证据
直接老牌 EDA 厂商既有工具:Synopsys DSO.ai、Cadence Cerebrus / ChipStack让买方在既有企业芯片设计流程中加入 AI 自动化已有出货产品、公开 AI 主张和老牌厂商账户控制力
相邻老牌 EDA 厂商Siemens Solido在定制 IC 和仿真工作流中竞争,AI 赋能表征已成为关键已有企业部署,但相对 Synopsys / Cadence 的完整数字实现流程,直接性更弱
直接初创公司Recursive Intelligence (Ricursive)承诺在半导体设计中提供更广的自我改进自动化融资规模大、团队精英,但没有公开客户或基准证据
开源替代研究脉络:AlphaChip / circuit_training让精英团队在内部复现部分布图规划栈软件免费,但范围窄、人才负担高
内部自建替代Google TPU、AWS Trainium、Microsoft Maia 团队显示先进买方可以靠第一方硅和私有工具链解决硬件瓶颈战略控制力极强,但只有最大的平台可行
现状替代NVIDIA 和 AMD 商用加速器通过采购而非定制设计解决眼前 AI 产能需求工作流变化最低,硬件生态最深
潜在进入者 / 资本磁石Cognichip、MatX、Rebellions在芯片设计自动化和相邻硬件领域争夺预算、人才和战略注意力2026 年资金充足,但多数比直接老牌 EDA 套件更早期,或更由硬件牵引

竞争格局按买方选择分组,而非严格产品分类;内部自建和商用硬件即便不是以 EDA 软件出售,也是在替代同一项待完成任务。

[CP005, CP008, CP009, CP010, CP018, CP022]
FP001: 竞争定位图

基于两条有证据支撑的轴做序数定位:分发能力和工作流控制广度;Recursive 野心评分高,但公开分发能力低于在位厂商和超大规模云替代方案。

评分是分析师的序数判断,锚定保留下来的采购权力、已装机工作流控制,以及不新增创业公司供应商也能解决买方问题的能力证据。

[CP014, CP022, CP025, CP035, CP041, CP043]

3.2 竞争对手画像显示,既有厂商赢在证明,创业公司主要赢在叙事

Synopsys 和 Cadence 是最强的直接竞争者,因为它们的 AI 产品已经被包装成现有企业流程的延伸。DSO.ai 被描述为自主 RTL-to-GDSII 优化,并可通过 AWS 走云部署路径。Cerebrus 被描述为 AI 驱动的流程优化,ChipStack 又围绕自主设计和验证加入明确的智能体式叙事。Siemens 不算直接的全流程数字签核对手,但仍重要,因为 Solido 用 AI 工具解决定制 IC 变异、仿真和表征,并已有企业安装基础。这些既有产品合在一起意味着,买方测试 AI 辅助芯片设计时,不必暂停既有信任或采购标准。 Recursive 的公开差异化是更大的野心:一个自我改进平台,意在压缩比点式优化器更多的设计周期。公司也通过 AlphaChip、RL-CCD、Insta、C3PO,以及此前在 Gemini、Claude、Grok 和 TPU 上的工作,拥有异常强的创始人与市场匹配度。可是公开记录在买方最在意的地方仍很薄。保留资料里没有任何一项说出 Recursive 客户、流片基准胜利,或与 DSO.ai、Cerebrus、ChipStack、Solido 的公开前后对比。定价在创业公司和既有厂商之间同样不透明,因此公开比较必须看范围、工作流契合度和证明,而不是标准化合同经济性。 新进入者群体更早。Cognichip 最接近直接设计自动化新进入者,因为它在推销 AI 帮助设计芯片。MatX 和 Rebellions 更相邻:两者都由硬件主导,可以争夺预算或战略注意力,却不提供同一软件层。这让它们不像 Recursive 那样是直接功能竞争者,但仍然重要,因为每一美元、每一名工程师、每一场被引向硬件替代方案的路线图讨论,都会让新的自动化供应商更难主导客户对话。[CP005, CP006, CP007, CP008, CP009, CP010]

竞争对手画像表
竞争对手类别规模 / 融资目标客户产品范围定价策略
Recursive Intelligence直接初创公司在 $35M 种子轮后,以 $4B 估值完成 $300M Series A先进设计团队、前沿 AI 实验室、追求定制硅的公司面向半导体设计的自我改进 AI 平台未披露靠全栈自动化广度和创始人履历取胜
Synopsys DSO.ai 产品直接老牌 EDA 厂商市值约 $83.70B;TTM 收入约 $8.00B现有 Synopsys 数字设计客户自主 RTL-to-GDSII 优化未披露通过把 AI 嵌入可信流程来防守装机基础
Cadence Cerebrus / ChipStack直接老牌 EDA 厂商市值约 $102.91B;TTM 收入约 $5.52B现有 Cadence 实现和验证团队流程优化,加上智能体式设计和验证未披露从优化扩展到更广的智能体式工作流控制
Siemens Solido相邻老牌 EDA 厂商上市工业软件老牌厂商;数千名设计师使用定制 IC、变异、IP 验证、仿真团队AI 赋能的定制 IC 设计和表征栈未披露占住 AI 已经发挥作用的相邻定制 IC 工作流界面
Cognichip可能的直接进入者2026 年 4 月融资 $60M探索 AI 协作助手的芯片设计组织面向芯片设计辅助的深度学习模型未披露主打成本和周期阶跃式下降的主张
MatX相邻硬件进入者2026 年完成 Series B关注 LLM 硬件吞吐量和延迟的买方LLM 芯片和硬件平台,不是 EDA 软件硬件 / 合同条款未披露争夺硬件预算,而非设计工具席位数
Rebellions相邻硬件进入者2026 年 3 月完成 $400M pre-IPO 融资推理基础设施买方垂直整合的 AI 推理基础设施硬件 / 平台定价未披露把需求拉向交钥匙 AI 基础设施,而不是定制设计

画像行把直接软件对手和相邻进入者放在一起,因为公开买方选择常常包括:给新工具拨款、 内部自建,或改为购买更多硬件。

[CP002, CP012, CP013, CP026, CP028, CP035]
能力 / 定价对比表
采购标准RecursiveSynopsys DSO.ai 产品Cadence Cerebrus / ChipStackSiemens Solido开源 / 内部自建
工作流广度声称提供全栈递归改进循环后端 / 全流程优化优化,加前端智能体式设计和验证定制 IC 变异、仿真、表征要么是范围较窄的开源布图规划,要么是完全私有的内部栈
公开自主或智能体式主张部分——AI 赋能,但未包装成完整的智能体超级代理开源方法或私有内部工具,不是公开打包的智能体
企业部署足迹尚无公开证据在定制 IC 相邻领域有仅适用于已经具备顶尖内部能力的团队
定价披露未披露未披露未披露未披露开源免费;内部自建消耗资本开支和工程预算
保留证据集中的公开客户或基准证据未具名有产品主张和 AWS 部署证据,但此处未保留具名基准胜利有产品主张和 ChipStack 发布主张,但此处未保留具名基准胜利有已部署使用主张,但没有保留与 Recursive 直接对标的基准仅有内部或研究证据
最适合买方想要广泛自动化、但没有超大规模云厂商级内部自建能力的团队现有 Synopsys 账户现有 Cadence 账户定制 IC 工作流负责人研究能力很强的精英设计团队或超大规模云厂商

该对比受证据边界约束:标为未披露或缺乏证据的单元格,反映公开来源限制, 不等于产品确定不存在。

[CP005, CP007, CP008, CP009, CP010, CP017]
FP002: 功能广度 / 能力图

矩阵视角对比各替代方案公开声称的广度、智能体式工作流、证明和买方匹配度;该图聚焦范围而非采用摩擦,是定价表的补充。

单元格只概括留存的公开证据;「留存证据中有限」意思是本章未保留标准化公开基准或具名客户案例,并不表示这类证明在任何地方都不存在。

[CP007, CP009, CP010, CP017, CP022, CP028]

3.3 切换成本、分发和供应通道仍偏向既有厂商与替代品

公开包装对比是不对称的。Synopsys 把 DSO.ai 与 AWS 部署基础能力配在一起,例如 ParallelCluster、Batch 和调度器支持,这意味着现有 Synopsys 客户可以扩展到 AI 优化,而无需重构运营模式。Cadence 强调复用设计师工作台,以及调用底层 Cadence 工具的智能体层,这同样把买方留在既有厂商环境内。Siemens 的适用面更窄,但只要定制 IC 表征或变异感知设计已经标准化,它仍能受益于既有企业位置。 相比之下,Recursive 要求买方在公开记录尚未展示成熟半导体采购部门通常想看的信任工件之前,先增加一个新供应商。公开材料没有披露定价、客户名称、合规姿态或带基准的部署。这不证明创业公司没有这些资产;它只意味着外部尽调还不能把它们视为已经验证。结果是切换成本劣势,即便产品命题比既有厂商点式工具更宽。 替代品在采用摩擦上表现不错。开源 AlphaChip 工具在软件意义上免费,但在人才和实验上昂贵。超大规模云厂商内部自建运营负担重,却能让最大买方获得最大控制权。NVIDIA 和 AMD 的商用加速器最容易采用,因为采购可以解决眼前 AI 容量问题,而不用开启新的设计流程。因此,Recursive 不只是要卖更好的自动化,还必须给出理由,让客户愿意承受比既有厂商延伸或更简单硬件采购路径更高的切换摩擦。[CP018, CP022, CP025, CP026, CP027, CP030]

切换成本 / 分销 / 供给访问表
替代方案锁定路径切换摩擦分销 / 渠道权力供给或算力访问对 Recursive 的净影响
Recursive新工作流和新的供应商信任关系在定价、支持和证据公开前都高未保留公开企业渠道证据取决于客户采用和伙伴建设需要更强的信任材料来平衡雄心优势
Synopsys DSO.ai 产品现有 Synopsys 流程、支持和云部署路径Synopsys 账户切换摩擦低很高——成熟的企业采购和 AWS 路径软件加可扩展云 / HPC 部署在 Synopsys 已经掌握流程的账户中,是最难撬动的直接现有厂商
Cadence Cerebrus / ChipStack现有 Cadence 设计和验证环境Cadence 账户切换摩擦低很高——根深蒂固的设计流程足迹围绕现有工具栈打包的软件能在初创公司试点赢得信任前防守账户
Siemens Solido相邻定制 IC 工艺和仿真工作流Solido 已标准化的场景中为中等在其细分企业市场中较高既有栈内的表征和仿真诀窍扩大了初创公司必须绕开并集成的老牌厂商界面数量
开源 / 内部自建内部专长和专有数据人才和算力负担很高没有渠道;取决于内部能力需要顶尖工程和算力资源主要只适用于技术最强的买方
商用硅硬件采购和生态熟悉度工作流变化最低借 NVIDIA 和 AMD 生态,渠道力量极强通过硬件渠道获得即时算力供给对不需要定制硅的买方,是最强现状替代

供给访问在这里宽泛理解为买方获取设计能力或算力容量的最容易路径;不限于实体晶圆分配。

[CP022, CP025, CP026, CP027, CP030, CP031]

3.4 护城河有可能成立,但公开反向证据仍主导持久性分析

Recursive 确实具备形成可防守位置的要素。AlphaChip 谱系是真实的,创始团队的领域匹配度异常高,公司也融到足够资本来积极招聘。如果它能把这些履历转成一套工作流,帮助团队压缩更多芯片设计周期,尤其是那些太小、无法自建超大规模云厂商级内部系统的团队,它可能在既有 EDA 套件和自建替代品之间占据有意义的位置。 问题在于,同一组创造可信度的证据也限制护城河持久性。AlphaChip 的开源谱系意味着技术栈的一部分可被检查,也可能被复现。New Scientist 的批评说明,关于强化学习在芯片布局中更优的主张,公开证明门槛仍然很高。与此同时,Synopsys、Cadence、Siemens 和行业观察者都指向一个世界:智能体式 AI 变成标准 EDA 功能,而不是创业公司独有差异化。如果这在 Recursive 发布客户胜利或基准证据之前发生,既有厂商可以把 AI 打包进受信任工作流,压缩创业公司建立溢价位置的窗口。 2026 年融资周期并没有降低风险,反而加剧了风险。Cognichip、MatX 和 Rebellions 显示,资本仍不断涌入设计自动化新进入者和相邻硬件公司。因此,Recursive 的护城河目前更多是理论而非公开证明:吸引力来自谁在打造它、它声称自动化什么;但它仍易受商品化、内部自建、硬件采购替代或既有厂商捆绑的冲击。[CP003, CP013, CP015, CP016, CP028, CP029]

FP003: 护城河 / 就绪度 KPI

截至 2026-07-03,Recursive 竞争就绪度和该品类外部压力的紧凑指标。

[CP033, CP034, CP038, CP039, CP040, CP050]
Chapter 04

04财务

4.1 收入模型、定价与 GTM 动作

Ricursive 的公开商业故事,形状比金额清楚。TechCrunch 称公司在构建设计芯片的 AI 工具,而不是芯片本身;Lightspeed 和公司则描述一个用于 AI 驱动半导体设计的全栈平台。这指向设计软件变现模型,而不是芯片销售:最可能的收入表面,是企业平台许可、设计伙伴项目,以及类似成熟 EDA 厂商的经常性支持或维护层。公开资料没有披露这些收入流今天哪一个已经存在、收入是一次性预付还是随时间确认,也没有披露是否已有客户为生产使用付费。 GTM 动作也高度定制。TechCrunch 报道称,Nvidia、AMD、Intel 和其他芯片制造商都是目标客户,Ricursive 不会点名早期客户,创始人可以选择首批开发伙伴。这与自助式 SaaS 漏斗正相反。它暗示公司要进入半导体设计组织,做长周期、技术密集型销售;可重复的经常性收入出现前,很可能需要试点、验证和实施工作。Ricursive 自有页面和已审阅媒体报道都完全没有公开定价,因此最能支撑的结论是:如果商业化已经开始,它也是报价制、伙伴主导,而不是广泛产品化。[CI005, CI006, CI007, CI008, CI014, CI017]

收入流表
收入流机制可能计费单位当前公开状态收入质量判断尽调要求
核心设计平台面向 AI 驱动芯片设计和优化的企业软件平台平台许可或年度合同平台已公开;变现形式未披露如果嵌入客户设计工作流,收入质量可能较高,但当前合同模式未知提供标准 MSA、定价表和首批已上线付费部署
设计伙伴合作与早期半导体客户开展深度试点或联合开发试点 SOW 或里程碑合同开发伙伴打法已公开;未披露合同金额如果收入依赖定制工作,质量低于经常性软件提供付费试点数量、平均合同金额,以及转为经常性收入的情况
验证和工作流自动化模块覆盖布局到设计验证的自动化模块、席位或工作流合同产品范围已公开;模块级打包尚未公开可提升挂载与扩展,但该流不是单独可观察的收入流披露模块打包、追加销售路径,以及验证是否单独收费
支持 / 维护层持续模型更新、工作流支持和缺陷修复,类似成熟 EDA 厂商支持期限或经常性维护费未找到 Ricursive 公开支持定价或政策若写入合同,可提升收入耐久性;目前只是推断出的未来层提供支持分层、续约条款和支持业务毛利率
计算支撑的设计运行公司或客户出资的计算资源,用于训练、调优或运行设计工作流按使用量、项目或预留容量计费计算扩张已公开;计费模式未公开如果计算过度打包进交付,毛利率可能被稀释说明训练 / 推理计算由谁付费,以及合同是否封顶或按量转嫁

各行把 Ricursive 今天公开描述的内容,与投资人需要在合同里看到的变现层拆开;未披露字段明确留空,而不是推断补齐。

[CI005, CI007, CI014, CI018, CI019, CI023]
定价 / 变现表
产品或类比对象公开价格 / 单位公开合同线索标价与实际价格来源视角 / 含义
Ricursive 核心平台未披露公开价格表或合同条款标价和实际成交价均未知Ricursive 对外材料讲的是使命和平台范围,不是商业条款
Ricursive 开发伙伴项目未具名早期伙伴意味着个案谈判实际项目经济性未知TechCrunch 暗示其企业销售由伙伴牵引,而不是发布标准 SKU
Synopsys DSO.ai 产品官方页面强调结果和工作流适配,不给公开标价外部很难看清企业价格发现过程支撑一个判断:AI-EDA 工具通常靠报价式企业谈判售卖
Cadence Cerebrus AI Studio官方页面营销 5X-10X 生产率提升,但没有发布费率表标价到净价的经济性未公开可作为企业价值销售的参照,而不是透明按量定价的参照
Siemens Solido 定制 IC 工具官方页面营销平台广度和 AI 加速,不给标价商业结构在公开层面不透明成熟类比公司也隐藏价格,说明 Ricursive 的不透明在品类上有一定一致性

空价格单元格表示在已审阅材料中没有找到公开价格。本表讨论商业不透明度,并不假设 Ricursive 内部没有定价。

[CI018, CI026, CI027, CI028]
GTM / 销售效率代理指标表
代理指标公开数值 / 信号置信度重要性尽调要求
目标客户群Nvidia、AMD、Intel、其他芯片制造商,以及需要芯片的公司确认其买方是企业级半导体客户,而非消费者或 SMB 用户按细分市场提供管线,并按客户类别提供平均交易规模
销售动作高触达的开发伙伴与企业销售动作复杂销售往往拉长周期,并推高解决方案工程成本提供试点到生产的漏斗、SE 参与度和中位销售周期
已具名付费客户没有具名或计数客户,就无法测试市场采用和客户集中度提供当前付费客户数、头部账户和各设计项目阶段
早期需求信号创始人称他们听到了每一家大型芯片制造商的声音,也能挑选首批伙伴显示市场好奇心,但不是收入转化提供已签 LOI、付费试点数量和按阶段划分的积压订单
公开 CAC / 回本期 / NRR没有这些指标,传统销售效率承保无法开展提供 CAC、赢单率、回本期、续约和扩张数据
实施负担平台覆盖从布局到验证的流程,且很可能仍需人工监督服务交付负担可能显著推迟软件式毛利率提供每个账户的可计费与不可计费工程时间,以及实施范围
商业基准密度无公开定价、无客户 logo、无已入账收入指标限制外部验证销售效率或变现速度的能力提供董事会汇报使用的商业 KPI 材料

本表使用代理指标,因为 Ricursive 没有公开传统 SaaS 或企业软件效率指标。空值反映披露缺口,不代表分析无关。

[CI006, CI008, CI020, CI021, CI032, CI040]
FI001: 收入模型桥

公开买方兴趣如何转化为 Ricursive 收入;未知的商业节点保持显式。

该流程只映射公开商业模式逻辑,不假设任何具体定价、试点转化率或确认收入分成。

[CI005, CI006, CI007, CI019, CI020, CI043]

4.2 成本结构、利润率路径与服务交付成本

公开证据暗示,Ricursive 的成本基础远重于普通软件公司,但轻于半导体制造商。Ricursive 的 Series A 公告称,融资将用于扩大研究和工程团队,并显著扩充算力基础设施。Lightspeed 认为,领先芯片设计仍要消耗大型工程团队、昂贵 EDA 工具和多年劳动。Siemens 和 HCLTech 补充了这份负担为何重要:3D IC、chiplet、先进封装和受信任工具链,会增加流片前所需的仿真、验证和可靠性工作量。即便 Ricursive 从不拥有晶圆厂或库存,它仍要为顶尖人才、算力、工具和面向客户的验证支持付费。 这套成本结构重要,因为利润率路径还不可观察。成熟上市可比公司展示了成功后的样子:Synopsys 和 Cadence 报告的软件、IP、维护和服务占比较高的收入模型,Synopsys 申报文件也暗示毛利率在高 70% 区间。但 Semiconductor Engineering 2026 年小组讨论是关键反向证据。它认为 AI 正在自动化繁琐设计任务,而不是直接替代 EDA 工具或人工监督;它还警告,全自动仍差一步,因为芯片设计错误极其昂贵。对 Ricursive 而言,这意味着近期服务交付很可能包含人在回路的设计、验证和工作流调优;在产品化被证明之前,毛利率会低于最终纯软件愿景。[CI009, CI011, CI012, CI013, CI022, CI023]

成本结构 / 毛利率驱动因素表
成本桶公开证据毛利率含义公开状态尽调要求
顶尖 AI 与半导体人才Lightspeed 称人工是半导体研发支出的主体;Ricursive 正在扩张一支小而精的顶尖团队在收入可重复、软件占比更高之前,短期毛利率会被压低强支撑按职能提供人数、全成本薪酬,以及按季度拆分的招聘计划
计算基础设施Series A 募资用途明确包括大幅扩张计算能力若计算未单独定价或未高效利用,打包计算会稀释毛利率强支撑提供计算预算、资本开支与运营开支拆分,以及客户费用分摊政策
EDA 与工具链费用传统 EDA 许可证被描述为昂贵,品类权力仍高度集中在 Ricursive 能替代或降低对既有工具依赖前,交付成本会被抬高方向性支撑提供年度第三方工具支出,以及按工作流阶段拆分的依赖度
验证与人在环审核TechCrunch 称平台延伸到设计验证;Semiconductor Engineering 称人工监督仍然必要增加解决方案工程和 QA 成本,推迟纯软件毛利结构强支撑提供实施手册、审核小时数,以及每个项目的缺陷 / 返工负担
先进封装与可靠性复杂度Siemens 和 HCLTech 描述了 3D IC、chiplet 与可信工具链复杂度持续需要仿真、可靠性和客户定制验证能力方向性支撑说明 Ricursive 原生支持哪些封装 / 可靠性工作流,哪些依赖伙伴
GTM 与解决方案工程面向芯片团队的企业销售意味着售前技术工作很重销售效率取决于签约前需要投入多少技术人力从公开 GTM 证据推断提供 AE/SE 比例、平均售前小时数和试点支持成本

本表区分直接披露的成本节点与类比推导的压力点。没有公开来源显示 Ricursive 采用晶圆厂或库存型商业模式,因此不假设其承担这类成本。

[CI004, CI009, CI012, CI013, CI029, CI030]
FI002: 单位经济模型桥

从企业兴趣到续约的定性桥接,标出利润率模型仍缺失的位置。

公开来源没有提供 CAC、回本期、毛利率或续约数据,因此未知值用显式节点表示。

[CI020, CI021, CI032, CI033, CI043, CI048]
FI003: 财务估计区间

有来源支撑的 Ricursive 融资事实数字锚点,以及界定最终软件经济性的公开类比。

点事实以相同低值 / 高值展示。类比项只是背景基准,不是对 Ricursive 表现的估计。

[CI011, CI022, CI024, CI036, CI037]

4.3 公开牵引、指标缺口与资本充足性

最强的公开牵引信号是融资速度、创始人履历和技术可信度,而不是财务表现。Ricursive 披露已融资 $335M;TechCrunch 和 Crunchbase 报道称,公司不到两个月内从 $750M 估值的 $35M 种子轮,跳到 $4B 估值的 $300M Series A。PRNewswire 称新资金将投向团队扩张和算力基础设施;DeepMind 的 AlphaChip 历史和 TechCrunch 关于主要芯片制造商兴趣的叙述,也解释了投资人为何愿意如此激进地给团队融资。这些都是真实的市场信念信号,但不能替代收入、定价或留存。 私有指标缺口仍是本章核心阻断点。已审阅公开资料没有披露收入、ARR、当前客户数、具名付费账户、毛利率、现金、烧钱速度、跑道或债务。即便下一轮触发条件也不透明:公开证据表明现金正在投向研究人才、算力和平台建设,但没有说明花得多快,也没有说明对应哪些商业里程碑。相对晶圆厂或云基础设施创业公司,Ricursive 的资本强度较低,因为它没有公开建设工厂或购买库存;相对普通软件创业公司,它仍然明显资本密集,因为算力和稀缺半导体人才处于交付中心。公开看,公司为研究加速融资充足,但还不能据此承销收入持久性。[CI003, CI009, CI010, CI016, CI036, CI037]

资本充足性表
项目公开数值 / 状态重要性证据质量融资含义尽调要求
已披露融资总额$335M定义今天公开可见的外部资本缓冲上限按初创公司标准很强,但仅凭这一点不足以推断可支撑月数提供交割后现金桥和当前非受限现金
种子轮融资2025 年 12 月初以 $750M 估值融资 $35M显示 Series A 之前投资人兴趣形成得有多快意味着估值加速早于广泛公开商业证明提供确切种子轮交割日期、股权结构表和任何老股转让
Series A 融资2026 年 1 月以 $4B 投后估值融资 $300M最大的公开硬融资事实,也是当前估值锚降低短期偿付担忧,但不降低商业化风险提供募资用途和现金目标的董事会材料
官方募资用途扩大研究 / 工程团队,并显著扩张计算基础设施说明资金投向研发和平台建设暗示资本需求绑定产品化和计算,而不只是 GTM 扩张按招聘、计算、工具和客户交付提供支出计划
账上现金公开未披露可支撑月数和下行情景耐受度的核心输入缺口置信度高,数值置信度低无法测试流动性或可支撑月数提供最新现金、受限现金和已承诺云 / 计算义务
烧钱与可支撑月数公开未披露稀释时点和融资依赖的必要输入缺口置信度高,数值置信度低无法承保下一轮时点提供基础 / 下行情景下的总烧钱、净烧钱和可支撑月数
债务 / 项目融资 / 租赁未识别到公开明细表杠杆可能显著改变企业价值和下行风险缺口置信度中可能代表资产负债表干净,也可能只是义务未披露提供债务、租赁、供应商融资和约束条款明细表
下一轮触发点未公开披露;可能与产品化里程碑、计算扩张或商业转化放缓相关解释当前轮次是桥接资本还是长周期资本中低无法从公开证据预测稀释触发点提供董事会定义的最低现金政策和融资触发阈值

本表关注前瞻资本充足性,而不是重复叙事型融资时间线。类似空值的条目是真实披露缺口,不是可轻易公开查到的占位。

[CI003, CI009, CI036, CI037, CI038, CI039]
公开牵引力 / 私有指标缺口表
指标或数据集公开内容缺失内容承保影响具体尽调路径
收入 / ARR / 签约额无公开收入数字;公开内容只有融资和战略按收入流拆分的当前收入、签约额,以及收入确认桥无法承保规模、增长或收入质量索取过去 12 个月收入、管线转化和会计备忘录
定价 / 合同价值无公开标价或实际合同价值标准定价表、试点定价、折扣政策和服务范围无法把客户兴趣映射为变现效率索取标准订单、价格表和前十份实际合同
客户名称 / 数量 / 集中度来自主要芯片制造商的未具名兴趣;无具名付费账户当前客户、试点数量、头部账户组合和集中度无法测试采用广度或单一客户依赖索取客户名单、各账户阶段和前十大收入占比
毛利率 / 交付成本只有公开可比公司披露毛利率结构Ricursive 毛利率、计算分摊、服务负担和支持成本无法判断商业化是软件式还是服务偏重索取按合同类型拆分的毛利率桥
现金 / 烧钱 / 可支撑月数已公开融资 $335M;当前流动性未披露当前现金、总烧钱、净烧钱,以及基础 / 下行情景可支撑月数无法判断融资紧迫性或下行韧性索取月度现金桥和 18 个月运营计划
商业证明点创始人履历、AlphaChip 传承和投资人阵容已公开已入账试点、生产账户、设计定点、续约,以及经过基准测试的客户结果公开牵引力更多靠可信度,而不是 KPI索取包含定价、周期时间和留存结果的客户案例
人数与职能组合公司称正扩张一支小而精的顶尖团队,但未公开人数或组合按季度拆分的工程、研究、解决方案和 GTM 人数无法建模固定成本增长或支持杠杆索取组织架构图、招聘计划和按职能拆分的流失数据

本表有意以缺口为中心,因为公开证据在运营指标上异常稀薄。每行都指向最低限度的私有材料,只有拿到这些材料,尽调才能从叙事走向财务承保。

[CI017, CI018, CI021, CI038, CI040, CI041]
FI004: 资本强度 / 现金流图

在经常性商业证明可见前,已披露资本可能如何流向研究、算力和产品化。

这是战略资本图,不是现金流量表。公开来源未披露 Ricursive 当前资产负债表或月度烧钱。

[CI009, CI038, CI039, CI045, CI046]

4.4 财务结论与尽调阻断点

财务结论既不是看空概念,也无法让承销安心。如果 Ricursive 成熟为关键任务设计平台,并拥有类似上市 EDA 厂商的经常性软件、IP、维护和服务经济性,收入质量可能变得有吸引力。问题是,公开证据还没有证明这些层级中任何一个已经规模化存在。没有披露价格本、没有收入确认政策、除了未具名兴趣外没有客户证明,也没有证据显示人在回路的设计和验证成本已经压低到足以支撑软件式利润率。 $335M 融资垫子降低了资本依赖,但问题仍未解决,因为现金、烧钱速度和跑道都未披露。最可能的失败模式不是晶圆厂过度建设,而是漫长且昂贵的产品化周期:算力、工程和客户交付成本跑得比可重复企业收入更快。核心尽调阻断点很直接:已签客户合同、当前 ARR 或已预订试点收入、定价和实施范围、支持负担、毛利率桥,以及当前现金与烧钱模型。在这些材料可得之前,仅基于公开资料的正确结论是:Ricursive 是一个资本充足的研发平台,最终经济性有希望,但当下商业化仍未验证。[CI017, CI018, CI020, CI032, CI034, CI035]

Chapter 05

05产品与技术

5.1 用客户工作流定义产品

今天最适合把 Ricursive 理解为高触达芯片设计平台加服务项目,而不是已经出货的商用芯片 SKU 或自助式 SaaS 产品。创始人描述的未来是:拥有规模化算法或工作负载的客户,把工作负载需求、目标约束和部署目标交给 Ricursive;Ricursive 再用 AI 压缩从架构选择到物理实现、最终到可制造 GDSII 交付的路径。公开表述反复把它框定为从 fabless 走向 designless:没有大型内部芯片团队的买方,应能购买定制芯片结果,而不是自己搭建完整设计组织。可见产品表面仍很早。官网主要是使命页;招聘和 Ashby 页面比公开文档更清楚地暴露建设方向,活跃招聘覆盖 EDA、RTL 验证、LLM 基础设施、软件基础设施、研究和安全。这一组合意味着,当前产品边界既包含单阶段设计加速器,也包含把它们运营起来所需的模型训练、验证和安全系统。[CE001, CE005, CE006, CE007, CE008, CE016]

产品 / 工作流表
用户任务当前工作流痛点Ricursive 解决方案层预期收益当前限制
AI 实验室 / 芯片团队需要面向特定工作负载的硅传统定制芯片项目需要大规模专家团队和超过一年的周期由项目牵引的 AI 芯片设计平台,从工作负载定义走向实现为规模化工作负载更快拿到定制硅尚无公开证据证明其已有经常性打包产品或稳定流片节奏
超大规模云厂商或芯片制造商想加快架构到版图迭代物理设计和验证循环缓慢且人力密集Phase I 阶段加速器,覆盖架构、时序、PPA 和临近签核任务缩短迭代循环,扩大设计空间探索公开基准包有限,且大多来自管理层描述
公司缺少内部芯片专家,但服务大型算法现成芯片可能并不适合专用工作负载无设计团队模式,由 Ricursive 为客户完成设计工作不组建完整芯片团队也能拿到定制芯片晶圆厂、支持和商业打包仍不透明
研究或基础设施团队想要更好的芯片 / 版图基础原语手工布图规划和布局仍难自动化将源自 AlphaChip 的 RL 与图模型传承用于设计子问题在选定布局任务上,把周或月压缩到小时技术传承已被证明;Ricursive 平台广度尚未得到独立验证
企业买方评估可信部署需要向供应商共享敏感工作负载和设计意图招聘信息暗示其正在推进安全、支持和治理工作流未来可能形成可审计运营模型未看到公开信任中心、SLA 或认证材料包

各行综合了公司官方定位和第三方报道;描述的是公开工作流承诺,不是经审计的客户流程图。

[CE005, CE006, CE007, CE008, CE015, CE031]
模块图谱
模块 / 资产主要用户状态 / 成熟度差异化尽调缺口
使命 + 官网定位潜在客户 / 投资人公开且当前有效把 Ricursive 描述为一家推动芯片设计递归改进的前沿 AI 实验室使命文案很宽,不是功能规格
AlphaChip 研究传承内部建模栈 / 可信度界面历史上已证明的上游资产TPU 项目中的生产证据让 Ricursive 比从零起步的初创公司更有可信度Ricursive 未公开说明这条传承有多少已经产品化、多少只是启发
Phase I 阶段加速器芯片设计客户团队已公开描述,但未公开打包瞄准多个设计阶段,而不只做布图规划无公开 SKU、定价或按模块拆分的基准表
内循环设计引擎Ricursive 研究人员 / 客户项目已公开声称据称结合 AI 芯片设计工具和快速分析引擎公开组件边界和评估指标仍稀疏
Phase II 工作负载到 GDSII 模型没有完整芯片团队的客户仅路线图目标是把架构、版图和可制造交付压缩进一条流程无公开发布日期、设计规则披露或客户引用
安全 / 支持工作流安全负责人、基础设施团队、客户成功从招聘推断仍处早期搭建承认可信工作流和基础设施对客户 IP 很重要尚无公开信任或支持材料

这是公开表面的模块图谱;可能存在非公开内部服务,但无法从保留证据中推断。

[CE006, CE012, CE014, CE016, CE017, CE018]
FE002: 客户工作流 / 运营流程

公开工作流从定义工作负载开始,进入迭代式设计加速,再走向可制造交付。

该流程描述公开访谈暗示的运营模型;Ricursive 尚未发布标准客户手册。

[CE005, CE007, CE011, CE013, CE014, CE035]

5.2 架构与运营模式

公开披露指向一种运营模式:把已被证明的研究原语放在底层,再叠加更宽的端到端野心。Ricursive 的技术可信度始于 AlphaChip:Goldie 和 Mirhoseini 参与构建了一个强化学习布局规划系统,Google DeepMind 称该系统使用基于边的图神经网络,在网格上按顺序放置组件,并已用于生产 TPU 世代和外部芯片项目。Ricursive 自己的平台似乎沿着这一谱系向两个方向延伸。第一,Phase I 聚焦既有流程里的阶段加速器,包括从架构设计到物理签核的时序分析和 PPA 驱动优化。第二,公司称 Phase II 会把各阶段合并成从工作负载到 GDSII 的模型,也就是客户界面变成工作负载描述,后端处理架构探索、布局、验证和制造交付。这一系统边界远宽于 Synopsys DSO.ai、Cadence Cerebrus 或 Siemens Solido;后者都被描述为既有 EDA 流程内部的 AI 增强层。主要保留点是,Ricursive 尚未公开记录这套端到端技术栈的精确内部模型边界、人工复核节点或签核链条。[CE003, CE004, CE010, CE011, CE012, CE013]

架构组件表
层 / 组件角色公开证据关键依赖风险
工作负载 / 需求输入把客户算法和约束转成设计目标EE Times 和伙伴叙事描述了面向第三方的特定工作负载芯片设计客户必须暴露足够多的工作负载细节分享敏感工作负载数据的商业和隐私模型未公开
RL / 图模型传承为布局和版图优化提供学习到的先验DeepMind 和 GitHub 来源描述了 AlphaChip 与 circuit_training 机制来自既有芯片模块的训练数据,以及持续模型迭代Ricursive 尚未公开新领域迁移学习的边界
面向阶段的加速引擎在完整端到端自动化之前,先改善时序、PPA 和物理设计任务StartupHub 报道了时序分析和 PPA 优化方面的公司说法快速计算基础设施,以及与既有工具对齐的基准表现这些说法来自公司口径,尚未获得广泛独立基准验证
面向 GDSII 的端到端编排把架构到实现并入同一条流程EE Times 称,Phase II 会接收工作负载并输出 GDSII晶圆代工关系、设计规则处理、验证链条没有公开的签核方法论或制造伙伴名单
人工审查 / 可信工具链层让自主优化始终挂钩设计质量和风险控制行业对比资料强调受监督、可审计的工作流资深工程师、验证检查点和安全基础设施Ricursive 尚未公布自己的控制模型
交付与制造交接把优化后的设计推进客户或晶圆代工厂的执行路径EE Times 称,Ricursive 想帮助客户把芯片推过终点线晶圆代工准入,以及下游封装 / 测试生态供应准入和出口管制流程未公开

该架构根据访谈、研究脉络和行业类比重构;Ricursive 尚未发布技术架构文档。

[CE010, CE011, CE013, CE014, CE015, CE021]
FE001: 产品架构图

公开证据显示,其架构可能分层:从工作负载接入,到阶段加速器,最终走向可制造交付。

Ricursive 尚未发布架构文档,因此该栈根据访谈、官方定位和研究脉络重建。

[CE006, CE010, CE011, CE014, CE021, CE031]
FE003: 关键依赖图

为了兑现端到端论点,Ricursive 依赖工作负载访问、技术脉络、算力、人工审查和下游制造关系。

依赖图突出公开可见的卡点;这并不意味着 Ricursive 披露了内部技术栈中的每个供应商或工具。

[CE010, CE011, CE021, CE022, CE027, CE028]

5.3 部署、集成、可靠性、支持与路线图

Ricursive 当前部署模式看起来由项目牵引,而不是由产品牵引。EE Times 称首轮推出面向第三方的工作负载特定芯片设计,这意味着在形成可重复产品包之前,需要定制需求接入、架构界定,并与客户工作负载集成。公司自己的前向地图分三阶段:先加速既有设计流程,再交付从工作负载到 GDSII 的端到端协同设计,最后才追求递归自治。可靠性证据最强的地方是谱系,而不是 Ricursive 自己的公开部署:AlphaChip 已在 Google TPU 中经生产验证;StartupHub 报道称,Ricursive 展示过一个静态时序分析引擎,据称与商业工具的相关性超过 0.999,速度显著更高。这在方向上令人印象深刻,但仍是管理层呈现的证据,不是独立发布的基准包,也不是具名客户流片。支持姿态同样只能推断。此次审阅的官方材料里没有看到公开定价、API 文档、状态页或 SLA 入口,因此在 Ricursive 证明相反之前,买方应假设上线和支持模式是咨询式的。[CE007, CE011, CE012, CE013, CE015, CE031]

部署 / 支持 / 可靠性矩阵
触点当前公开状态可靠性 / 支持信号信任 / 质量信号缺口
Phase I 第三方合作公开表述为初始推出说明某种形式的客户侧部署已经开始没有公开 SLA、入门指南或支持组织披露需要具名客户阶段和合作结构
时序分析 / 阶段加速说法在 2026 年采访中公开提出据称与领先商业工具的 epsilon 相关性达 0.999+,速度超过 1000x没有公开基准方法包需要可复现的基准输入和独立验证
工作负载到 GDSII 的端到端路线图仅为路线图为更广的平台化给出清晰运行目标没有公开签核链条、QA 流程或设计规则合规叙述需要发布里程碑和治理检查点
官网与支持触点公开页面主要是使命页、招聘和媒体链接说明当前更像高接触支持,而非自助式产品交付没有公开文档门户、定价、API 文档或状态页需要客户实施文档和支持包
安全 / 隐私 / 合规姿态已发布 Founding Security Engineer 岗位;未披露正式项目承认需要专职安全负责人没有公开认证、隐私材料包或信任中心需要安全架构、数据处理和合规材料

可靠性信号混合了生产脉络证据和管理层 2026 年口径;它们不等同于独立的流片后验证。

[CE007, CE011, CE015, CE017, CE029, CE030]
FE004: 产品成熟度 / 能力图

公开证据最强处是研究脉络,最弱处是 Ricursive 特定部署证明和信任披露。

成熟度评级只综合留存公开证据,不是内部就绪度评分。

[CE004, CE012, CE019, CE029, CE031, CE038]

5.4 差异化、IP 与运营护城河

Ricursive 最清楚的差异化是范围。Synopsys、Cadence 和 Siemens 的既有 AI-EDA 产品,营销重点是优化或编排既有设计流程;Ricursive 营销的是一个未来:客户描述工作负载,收到可制造设计结果。这一定位可能具备战略意义,因为芯片设计周期仍以年和大型人工预算计,而即便一流商业工具,也大多是在传统工具链内部优化。第二个护城河组成部分是创始人和数据谱系:团队可以指向 AlphaChip、开源 circuit-training 资产和获奖后续研究,证明其理解学习问题,也理解物理设计约束。第三个组成部分,是围绕特定工作负载共同设计模型和硬件的运营经验,而不是销售现成加速器。不过,公开范围内的护城河仍更像承诺而非已证事实。Ricursive 没有公开披露专利组合、客户锁定指标、专有数据集规模或持久供应协议,因此尽调应把护城河视为技术上可信、商业上未证。[CE004, CE010, CE023, CE024, CE025, CE026]

差异化 / IP 护城河表
护城河维度公开证据重要性当前强度待解问题
创始人 / 研究履历官网点名 AlphaChip 创作者和获奖后续工作,第三方也有报道提高 Ricursive 解决高难度设计搜索问题的概率既有研究中有多少能在 Ricursive 内形成独有防线?
端到端范围对比既有 AI-EDARicursive 称自己不是 EDA 公司,目标是从工作负载直达 GDSII 的结果范围扩张可能把价值从工具优化推向完整芯片落地概念上强它能否在生产质量下超过既有签核流程,或围绕这些流程完成集成?
训练数据 / 循环效应GitHub 和 DeepMind 资料显示,AlphaChip 式学习会随着设计实例增多而改进解决的设计问题越多,模型质量应能复利提升Ricursive 尚未披露专有数据集规模或反馈循环
客户价值主张Designless 叙事瞄准没有大型内部芯片团队的买家可把 TAM 扩到传统无晶圆厂设计公司之外可复制客户胜利的公开证据仍然缺位
供应 / 制造交接EE Times 称,Ricursive 计划帮助客户把芯片推过终点线要真正交付,必须拿到晶圆代工和封装的运营通道不清晰未披露公开晶圆代工、封装或测试伙伴关系
信任 / 治理姿态已有安全招聘,但没有公开信任材料敏感客户工作负载和流片前 IP 需要强控制公开证据弱Ricursive 何时发布隐私、安全和 QA 标准?

本表区分技术可信度和已有商业证据的护城河;公开证明前者远强于后者。

[CE004, CE010, CE017, CE023, CE024, CE026]

5.5 信任、安全、安全防护、隐私、合规与质量控制

这是 Ricursive 故事里公开记录最弱的一块。关于智能体式 EDA 的行业资料持续强调人工监督工作流、受信任工具链、可审计性和质量控制,因为芯片设计错误会直接传导成昂贵的制造风险。相比之下,Ricursive 的公开材料还没有暴露信任中心、面向敏感客户 IP 的隐私声明、安全架构、认证清单、数据留存政策、模型治理说明或硅后质量框架。最接近的公开信号是 Ashby 招聘板,它在 EDA 和基础设施岗位旁列出创始安全工程师。这是正面信号,因为它说明公司知道安全必须早期内建;但它也表明控制面仍在招人,而不是已经通过成熟公开工件证明。Ricursive 的价值主张要求客户分享高价值工作负载,甚至可能分享硅前设计意图;缺少公开信任文档不是表面问题,而是真实尽调阻断点,应在风险敏感客户或投资人承销广泛部署之前补上。[CE017, CE018, CE020, CE027, CE028, CE029]

5.6 展示材料

Chapter 06

06客户

6.1 目标客户画像、买方 / 使用者 / 付款方地图与工作流位置

尽管公开记录不能支持一份公开客户名单,但它支持相当具体的客户形态。Ricursive 卖的不是成品芯片。它把芯片设计加速命题卖给那些已经背着昂贵芯片路线图、大额算力预算和痛苦 PPA 取舍的组织。这首先指向前沿 AI 实验室和超大规模云厂商,其次是大型 fabless 半导体供应商,再往后是因为推理规模或硬件差异化具有经济意义、如今足以支撑内部 ASIC 项目的系统公司。可见类比都在这个世界里:TSMC 庞大的晶圆代工客户群,AWS 和 Google 的定制芯片项目,以及正在优化先进制程 SoC 的 Cadence 和 Synopsys 客户。 一个账户内部,买方、使用者和付款方不太可能是同一个人。买方大概率是关心到流片时间和总系统经济性的算力、平台或芯片项目负责人。使用者更可能是待在 EDA 工作流里的物理设计、验证或架构团队。付款方则是为芯片路线图买单的更大企业预算负责人。这种分裂很重要,因为它意味着销售动作漫长且由技术中介,而不是轻量级产品驱动采用。Ricursive 自己的招聘板也强化了这一判断:公开招聘仍集中在 EDA 算法、基础设施、验证、研究和安全,而不是现场销售或规模化客户成功。 Sequoia 的 “designless” 表述也有信息量。卖点不只是让现有芯片团队工作更快;而是更多公司可能成为芯片买方或芯片项目发起方,却不用搭建巨大的内部设计组织。如果这一命题成立,Ricursive 的 TAM 可以从传统 fabless 供应商扩展到 AI 实验室和系统公司:它们想要定制芯片,但不想从零复制一套 Broadcom、Google 或 NVIDIA 式芯片组织。不过,这仍是目标客户假设,不是已经被证明的 Ricursive 业务账簿。[CU002, CU003, CU004, CU005, CU006, CU007]

客户分群表
客群买方主要用户付款方用例战略价值缺口
前沿 AI 实验室 / 超大规模云厂商计算、基础设施或芯片项目负责人物理设计、验证和架构团队中央基础设施或 AI 平台预算加速定制 AI 加速器设计和协同优化没有具名 Ricursive 账户或转化证明
大型无晶圆厂半导体公司工程副总裁或 SoC 项目负责人模块工程师和实现团队芯片项目 P&L缩短先进制程芯片的 PPA 迭代时间需要证明 Ricursive 在生产中胜过既有 EDA 自动化
拥有自研定制芯片的系统公司平台或硬件总经理内部 ASIC / 芯片团队公司产品预算在不快速扩充设计人手的情况下打造差异化芯片中高Ricursive 公开材料未显示系统公司部署
第三方设计服务 / 协同设计机构业务负责人或技术发起人EDA 和验证专家项目预算或客户出资的服务预算在多个客户流片中复用 AI 工具未披露 Ricursive 的公开设计服务合作
购买云端定制芯片的 AI 原生模型公司模型或基础设施负责人ML 系统和服务工程师模型训练 / 推理预算用设计自动化缩短与模型经济性绑定的定制芯片周期中高Ricursive 周边需求可见,但 Ricursive 的胜利未公开

这些客群来自公开工作流证据中最可支撑的买方原型,不是 Ricursive 披露的客户名单或收入结构。

[CU002, CU004, CU005, CU006, CU007, CU010]
FU001: 买方-用户-付款方与工作流图

Ricursive 可能卖入复杂企业硅项目,经济买方、用户和付款方并不相同。

[CU005, CU006, CU010, CU032]

6.2 公开证据栈:相邻可信度真实存在,Ricursive 自身客户证据仍然单薄

核心客户事实是负面的,但很重要:Ricursive 的公开页面没有点名生产客户。TechCrunch 更明确,称创始人不会点名早期客户。同一篇访谈确实报道了来自“每一家大型芯片制造商”的强烈主动询问,并称 Ricursive 可以挑选首批开发伙伴;这比零信号更好,但仍明显弱于具名账户、买方引述、流片案例或结果指标。发布新闻稿中的“早期企业”表述也应归入同一桶:它显示商业化意图,而不是客户证明。 更强的是相邻谱系。DeepMind 称 AlphaChip 已用于多个 TPU 世代,MediaTek 也将其扩展到先进芯片。Sequoia 播客补充说,创始人数年来把 TPU 团队视为内部客户,并围绕这些工程师真正关心的指标打磨方法。这很有意义,因为它证明她们过去解决过真实设计用户问题。但它仍是相邻证明,不是 Ricursive 收入证明。正确解读是:Ricursive 一开始就拥有异常强的创始人与市场匹配度,也拥有异常弱的公开牵引披露。 市场侧背景解释了投资人为何愿意容忍这一缺口。Anthropic、AWS、Google、Microsoft 和其他平台构建者已经在证明,当成本、吞吐和控制足够重要时,大买方会投入定制芯片路径。从这个意义上说,Ricursive 指向的是真实痛点。缺失的一步,是证明客户会把生产设计流程中有意义的一部分,交给 Ricursive 这家公司。[CU001, CU012, CU013, CU014, CU015, CU016]

客户增长 / 采用轨迹表
代理指标公开数值 / 状态日期信心含义缺失分母
具名 Ricursive 生产客户公开无具名客户2026-07-03公开牵引力证明仍薄底层客户数量未知
未具名早期客户创始人不愿透露名称2026-02-16中高说明已有某些账户活动或评估未披露阶段、logo 或用例
首批开发伙伴创始人称可以从中选择2026-02-16显示大型芯片制造商主动表达兴趣没有合同数量或范围
相邻已部署脉络AlphaChip 用于多代 Google TPU,并由 MediaTek 扩展2024-09-26创始人曾在相邻工作流上跑出规模不是 Ricursive 客户指标
目标市场的定制芯片需求Anthropic / AWS / Google TPU 承诺显示平台采用规模达数十亿美元2026经济性清晰时,大买家会投入不是 Ricursive 专属胜利的证据

这些是公开采用代理指标,不是 Ricursive 的直接客户指标;没有披露分母或 Ricursive 部署数量的缺口在表中保留。

[CU001, CU012, CU016, CU017, CU018, CU028]
具名客户证明表
参考对象与 Ricursive 的关系公开记录内容生产还是试点关键限制
未具名早期客户直接 Ricursive 信号TechCrunch 称创始人不会透露早期客户名称Unknown未披露标识、合同、用例或结果
未具名开发伙伴直接 Ricursive 信号TechCrunch 称大型芯片制造商主动接触,Ricursive 可以选择首批开发伙伴可能处于生产前 / 评估阶段没有伙伴名称、范围或买方引述
Google TPU 团队 / Google Cloud TPU 脉络相邻创始人证明AlphaChip 曾用于多代 Google TPU,TPU 产能也通过 Google Cloud 触达外部用户生产级相邻证明证明属于创始人过往工作,不属于 Ricursive 合同
MediaTek相邻外部采用者DeepMind 称 MediaTek 将 AlphaChip 扩展到先进芯片生产级相邻证明不是当前 Ricursive 收入账户的证据

该枚举有意混合直接 Ricursive 信号和相邻证明,因为公开的 Ricursive 具名客户证明缺位;区别逐行保留。

[CU001, CU012, CU014, CU015, CU016, CU017]
FU002: 公开证明阶梯

可见证据从相邻创始人证明延伸到未具名的 Ricursive 兴趣;具名 Ricursive 生产客户仍是明确缺口。

[CU012, CU015, CU016, CU017, CU038]

6.3 早期伙伴模糊性、渠道与采用约束

即便 Ricursive 赢下技术上令人印象深刻的试点,采用仍取决于一个公司无法完全控制的生态。Cadence 和 Synopsys 的证据显示,客户已经期待这些工具待在什么位置:完整数字设计流程内部,并与验证、时序和物理实现紧密互动。AWS 的 DSO.ai 案例研究又增加了一层实施要求,显示基础设施规模和自动扩缩容 HPC 集群在实践中很重要。TSMC 的专属代工材料从制造侧提出同一观点:严肃芯片客户购买的不只是单个优化引擎,还包括支持、客户管理、工程服务和生态兼容性。 客户侧约束也能在 Ricursive 之外看到。Omdia 的晶圆代工墙分析称,先进封装和 HBM 至少到 2027 年中仍是卡点。Morrison Foerster 的出口管制说明提醒读者,合规风险如今触及更广泛的 AI 芯片生态,而不只是晶圆厂和出口商。Data Center Frontier 的 Anthropic 画像显示,成熟实验室会主动在 Trainium、TPU 和 GPU 之间分散,以保住供应和价格谈判筹码。这种行为暗示 Ricursive 需要满足一项微妙但重要的客户要求:买方可能想要可移植性和互操作性,而不是把自己锁进单一云、单一晶圆厂关系或单一验证技术栈的工作流。 这就是为什么 TechCrunch 所谓“首批开发伙伴”一开始听起来重要,但实际没那么重要。开发伙伴有用,却不能回答谁拥有部署风险、谁签合同、谁支持流片,或当一个设计必须从有前景的试点走向商业芯片时,谁承担晶圆厂或出口延误。渠道质量和生态契合度因此是核心尽调议题,而不是旁注。[CU021, CU022, CU023, CU024, CU025, CU026]

扩张与集中风险表
扩张驱动因素集中或依赖风险影响尽调路径
旗舰账户中拿下标杆客户单个标杆客户可能主导叙事和议价权索取头部账户敞口,以及领先账户暂停时的情景分析
在更多芯片项目中先落地再扩张尚无公开证据显示一个试点能扩成多个生产项目中高审阅每个账户的项目数量和试点后的扩张历史
借云、晶圆代工或 EDA 生态的伙伴通道获客伙伴议价力会影响定价、支持和实施控制权审阅具名互操作或联合销售协议
更快流片或验证结果晶圆代工、封装和 HBM 瓶颈仍会拖慢终端客户价值兑现厘清哪些约束 Ricursive 能直接解决,哪些只能间接影响
全球客户覆盖出口管制和客户所在地可能压缩合法或实际可购买产品的人群获取客户地域、出口管制矩阵和受限使用政策

这些是围绕当前公开证据集的风险视角,不是按概率加权的收入预测。

[CU023, CU024, CU025, CU026, CU031, CU032]
FU003: 客户证明矩阵

相邻市场需求强,但 Ricursive 自身证明和持久性证据仍稀疏。

[CU011, CU018, CU021, CU023, CU026, CU034]
FU004: 从试点到生产的尽调路径

有说服力的 Ricursive 试点仍必须越过集成、流片、制造和扩展关卡,才能证明客户持久性。

[CU023, CU032, CU033, CU039, CU041, CU042]

6.4 持久性、集中度与仍需完成的尽调

耐久性是公开证据最薄弱之处。留存来源没有披露客户数、试点到生产的转化率、合同期限、NRR、GRR、续约节奏, 甚至没有清晰区分评估账户和生产账户。不能把这种缺失解读成失败信号;很多极早期基础设施公司都会把这些数字留在私域。 但这也意味着,本章不能仅凭创始人履历或融资速度,负责任地推断留存质量、扩张效率或安装基础健康度。 公开记录也无法测算集中度风险,这本身就是风险信号。公司可以拥有广泛的主动询盘, 却仍在商业上依赖一两个标杆设计伙伴,用于验证、路线图反馈和未来订单。如果 Ricursive 第一个可见参考客户最终是前沿 AI 实验室或顶级芯片厂商, 这个胜利会有战略价值——但也可能给客户带来谈判筹码,并扭曲公司的收入结构。管理层披露更多信息之前, 诚实做法是保留缺口,而不是用未公开的 logo、NPS 或留存说法去填补。 客户尽调因此要直接追问隐藏变量。最有决策价值的要求包括具名客户参考包、带转化状态的试点漏斗、脱敏合同结构、 在现有 EDA 栈中的工作流位置、流片或验证结果证据,以及已签客户和近期管线的集中度数据。Ricursive 可能确实在 NDA 背后拥有优秀早期客户。 当前公开记录只是还没有证明这一点。[CU027, CU028, CU029, CU030, CU031, CU038]

留存 / 重复使用 / 满意度表
指标数值 / 状态客群信心尽调请求
净收入留存(NRR)空值 — 未公开披露所有 Ricursive 客户按同期群索取账户级扩张和收缩情况
总留存 / 流失空值 — 未公开披露所有 Ricursive 客户索取试点和生产账户的续约与流失历史
合同期限 / 续约节奏空值 — 未公开披露所有 Ricursive 客户审阅 MSA 样本、试点协议和续约条款
试点到生产转化空值 — 未公开披露所有 Ricursive 客户获取带签署日期和转化率的管线阶段
工作流粘性代理指标集成 EDA / 晶圆代工 / 云工作流意味着切换摩擦可能很高,但对 Ricursive 还未证实可能是企业设计账户用客户访谈和重复流片使用证据验证粘性

空值表示公开记录未披露该指标;最后一行是推断代理指标,不应误认为 Ricursive 留存证明。

[CU028, CU029, CU032, CU039]

6.5 证据

Chapter 07

07风险

7.1 估值和商业证据是最大的剩余风险

Recursive Intelligence 公开品牌名为 Ricursive Intelligence,融资规模已经足以让市场按商业证据、 而不只是技术承诺来评估它。公司启动后数月内估值达到 $4 billion,但已审阅的公开材料仍围绕创始人、 AlphaChip 渊源以及压缩设计周期的愿景,缺少具名客户、公开基准或可重复经济性。这种错配很关键, 因为目标买家是大型半导体公司,资格认证周期长,内部团队强,也有能力等既有供应商补齐功能缺口。 因此,主要风险不是论点不自洽,而是估值已明显跑在公开证据前面,产品、转化或定价一旦打滑,容错空间很小。 在这种设置下,即使技术上亮眼的试点,如果不能足够快地转化为反复出现的生产级客户证据,也仍可能撑不起价格。 这里速度极其重要。[CR004, CR005, CR008, CR009, CR010, CR037]

按严重度排序的风险登记表
风险类别可能性影响缓解成熟度剩余敞口投资含义
商业证明 / 估值缺口财务 / 模型严重低中若没有具名生产伙伴、基准数据和清晰转化路径,不要为当前倍数背书。
既有 EDA 与工具链替代伙伴 / 依赖低中Ricursive 需要拿出证据,证明自己能嵌入认证流程,而不只是买家有兴趣。
AI 驱动设计的验证与可靠性短板运营 / 技术中高严重若无法证明签核级信任,收入会推迟,市场认知中的产品范围也会被压缩。
出口管制与跨境合规敞口监管 / 法律低中中高如果母公司筛查、远程访问或许可控制不成熟,全球账户准入会很快收窄。
算力消耗叠加漫长认证周期财务 / 模型若基础设施扩张快于客户验证或变现节奏,跑道会收紧。
创始人与精英人才集中人员 / 执行中高中高执行面必须先从小型、偏研究的核心团队扩展开来,平台才可能安全放大。

各行按剩余严重性排序,而非按时间顺序;它们概括了未来 12 至 18 个月最可能改变承销判断的风险。

[CR005, CR008, CR010, CR012, CR017, CR022]
财务 / 商业模型风险台账
风险当前公开信号仍缺什么可能性严重性剩余暴露投资含义
估值跑在公开商业验证前面上线数月内融资约 $335M,估值 $4B具名付费部署、基准化结果和转化数据严重入场纪律很重要,因为下一步验证必须来自商业结果,而不是叙事。
收入可见度出现前,计算基础设施烧钱先扩大公司称资金将用于扩大计算基础设施和精英工程团队烧钱、跑道、毛利率,以及托管 vs 本地部署成本模型在经济性更清楚前,资本强度可能更像基础设施研发,而不是轻量软件。
认证周期拖慢收入兑现目标买方是大型芯片制造商,签核和风险评审周期很长试点时长、评估标准和转为合同收入所需时间中高收入节奏可能滞后技术进展数个季度甚至更久。
既有厂商打包定价压力压缩变现EDA 套件已有七位数席位经济性和深厚企业关系Ricursive 定价、ROI 门槛,以及相对既有厂商附加模块的替代经济性中高中高即便产品不错,能拿到的经济租也可能低于当前估值假设。
商业化范围仍集中在少数先进芯片项目公开叙事指向顶级芯片制造商目标,而不是广泛的 SMB 式买方池管线集中度、头部账户占比,以及前沿 AI 芯片之外的备用需求中高中高中高少数项目推进慢或丢单,就可能不成比例地改写近期收入叙事。

本表拆出公开叙事目前还无法用直接分母闭合的经济假设。

[CR003, CR004, CR005, CR006, CR008, CR009]
FR001: 风险热力图

估值已经上台阶,但产品、客户和验证证明相对于在位替代方案与合规负担仍偏薄;这些位置的剩余风险最高。

序数评级概括保留的证据集,不是管理层指引,也不是概率预测。

[CR008, CR010, CR012, CR022, CR027, CR038]

7.2 监管、IP 和验证风险可能在收入跟上前拖慢部署

Ricursive 所在领域让跨境合规和技术信任越来越重叠。BIS 现在对先进计算许可更看重最终母公司所在地、 远程访问和文件证据,全球芯片设计公司不能把合规当成事后事项。与此同时,技术文献表明, AI 辅助芯片设计仍需要人工监督验证、可信工具链和谨慎的数据治理。支撑现代 AI 芯片的 3D-IC 和先进封装路线进一步抬高了风险, 因为热、电、机械问题可能很晚才暴露,届时返工昂贵甚至不可能。Ricursive 因而面对一组耦合风险: 法律、安全和验证弱点都可能拖慢设计伙伴转化、压窄商业范围,或把收入兑现时间拉长到当前估值所隐含的节奏之外。 半导体承载敏感 IP 和受出口管制影响的终端用途;这里的信任失败不是小产品 bug,而可能让整个账户失去资格。[CR020, CR021, CR022, CR023, CR024, CR025]

监管 / 法律风险台账
规则 / 案件 / 风险面司法辖区状态可能性严重性缓释措施剩余暴露尽调路径
针对 D:5 或母公司在澳门的实体的先进计算许可要求美国出口管制 / 全球账户BIS 指引仍有效,许可要求持续存在可通过严格筛查、许可办理和账户架构管理中高结合 BIS 筛查和许可流程,复核客户、分销商和合作伙伴的母公司映射。
授权 IC 设计商时间线,以及 BIS 到 2026 年前后的立场变化美国出口管制时间线延长至 2026-12-31,说明规则仍在变化中高持续跟踪 BIS 更新并记录产品分类,可降低突发风险获取出口管制备忘录,说明 Ricursive 的分类立场、获批设计商规则的关联性及升级流程。
面向跨境设计协作的远程最终用户和 IaaS 限制美国出口管制 / 托管工作流文档和远程访问负担已明显上升可用本地部署或严格受控的托管环境缓释中高检查任何试点或支持工作流是否允许远程访问受控设计工件或模型。
客户设计 IP、保密义务和责任分配私有客户合同 / 设计数据公开合同条款未披露,行业指引则强调可信工具链中高强内部控制可能有帮助,但公开法律确定性仍弱在承销受监管或主权客户之前,索取 MSA、IP 归属、赔偿、支持访问、数据留存和安全开发控制材料。

本表聚焦最可能影响账户资格、客户尽调或部署摩擦的公开法律与监管风险面,而非猜测性诉讼。

[CR025, CR027, CR028, CR029, CR030, CR040]
运营 / 质量 / 安全风险台账
失效模式可能性严重性缓释成熟度剩余暴露未解缺口
AI 智能体输出仍需人工监督验证,才能避免芯片无法工作中高严重需要一套基准包,说明自动化边界在哪里、哪些结果仍由人工签核负责。
3D IC 的热、机械和电气相互作用在流程中过晚暴露低中需要证据证明 Ricursive 能建模封装级多物理场,而不只是改进楼层规划层面。
面向 AI 的设计数据和 PDK 背景不完整、孤岛化或噪声大中高低中中高需要针对客户专属设计语料的数据摄取、血缘和模型治理材料。
流片或签核错误会造成不可逆的进度和成本损伤中高需要证明 Ricursive 如何接入晶圆厂认证的时序、DRC、PI 和 SI 工作流。
可信工具链、IP 安全和版本可追溯性低于买方预期中高需要拿出适合半导体 IP 所有者审查的安全开发、审计日志和支持访问证据。

当设计自动化主张靠验证严谨性、多物理场真实性和严格 IP 处理来支撑,而不只是靠模型新颖性时,运营风险最高。

[CR020, CR021, CR022, CR023, CR024, CR025]
FR002: 风险传导图

技术可信度、出口管制和安全工作流要求,会传导到部署节奏、现金消耗、收入转化和估值;传导速度比公司公开叙事暗示的更快。

该图突出一阶传导路径,而非列举所有可能的反馈回路。

[CR020, CR022, CR025, CR027, CR030, CR040]

7.3 既有 EDA 平台、晶圆代工认证流程和集中买方带来结构性依赖风险

Ricursive 正进入一个规模大但结构集中的市场。独立市场研究显示,AI EDA 和更广义的 EDA 栈已经由少数供应商主导; 官方产品页也显示,这些供应商正在把强化学习、智能体式、以验证为中心的自动化铺到设计流程的大部分环节。 这很关键,因为 Ricursive 需要的不只是兴趣,而是在已经掌握签核、晶圆代工资格认证和大量客户关系的既有系统里插入工作流。 买方同样集中。公开半导体分析显示,超大规模云厂商和大型芯片商正在开发自有 ASIC,并非常重视主权, 因此它们有吸引力,也很挑剔。依赖风险于是双向存在:上游依赖既有工具和合格流程, 下游依赖少数高度成熟、可以自建或等待的客户。这让商业门槛高于普通企业软件,因为 Ricursive 必须在客户已经从可信供应商购买打包 AI 的生态里取胜。[CR011, CR012, CR013, CR014, CR015, CR016]

合作伙伴 / 依赖风险台账
依赖项对手方 / 技术栈角色集中度失效场景严重性缓释措施剩余暴露
AI 辅助布局布线与优化栈Synopsys掌控靠近签核环节的 AI 工作流和大部分客户关系触面客户更愿意扩展既有 Synopsys 工具,而不是采用创业公司平台Ricursive 可以定位在既有流程之上或与之并行,但必须证明实际工作流优势
AI 驱动的 SoC 实现与验证栈Cadence在生产力、验证和智能体式前端自动化上直接竞争Cadence 很快补齐产品缺口,并打包进现有企业合同Ricursive 可以切入新的工作流切口,但打包压力会立刻出现
定制 IC 验证与多物理场生态Siemens掌握重要的定制 IC、仿真和 3D-IC 可靠性场景中高买方标准化到 Siemens 主导流程,把 Ricursive 视为冗余或有风险中高合作或互操作性会有帮助,但客户信任起点仍是既有厂商认证中高
晶圆厂认证签核与后端认证成熟晶圆厂和 EDA 流程所有者守住时序、DRC、SI、PI 和可制造性输出的最终验收关口没有被接受的下游流程,Ricursive 无法从试点洞察走到生产签核严重狭窄的辅助角色可以成立,但在签核集成得到证明前,全栈主张仍受限制
大型芯片制造商与超大规模云厂商客户群NVIDIA、AMD、Intel 及其他成熟半导体买方潜在客户也有强大的内部团队,且自研 ASIC 计划在增加买方用 Ricursive 做评估,但把核心诀窍留在内部,或等待既有厂商大客户能验证品类,但在 Ricursive 证明实质性切换价值前,议价权仍在客户手里

依赖风险是结构性的:Ricursive 夹在上游强势既有工具和下游少数技术成熟买方之间。

[CR005, CR011, CR012, CR013, CR014, CR015]
FR003: 依赖图

Ricursive 同时依赖既有工具栈、下游合格签核、稀缺人才,以及客户集中、且往往能自研的买方群体。

该图抽象出杠杆最高的依赖,而不是列出每一家供应商、客户或晶圆厂关系。

[CR011, CR013, CR014, CR015, CR016, CR018]

7.4 执行缓释因素真实存在,但论点仍由事件驱动

Ricursive 并非从零开始。创始人确有技术传承,公司已经吸引顶级资本,官方材料也显示工程和运营岗位在招聘。 这些缓释因素有意义,因为深度 EDA、验证和系统知识在这个类别里很稀缺。但它们只能降低风险,不能消除风险。 公司仍必须把小而精英的研究文化转化为可重复的产品交付、客户资格认证、安全工作流治理, 以及能在漫长企业设计周期里赢单的商业组织。因此,合理承保姿态应是有条件、由事件驱动。 投资人应观察具名伙伴转化、有基准的验证证据、出口管制准备度,以及一条与客户验证速度匹配的算力消耗资金桥。 上述信号出现之前,尽调不应过度聚焦宏大的市场规模愿景,而应更关注公司能否反复跨过资格认证、安全和工作流采用关口。[CR001, CR002, CR003, CR006, CR007, CR034]

人员 / 执行风险台账
角色 / 职能依赖或缺口可能性严重性缓释措施尽调路径
创始人主导的产品与技术愿景公开叙事高度锚定 Anna Goldie 和 Azalia Mirhoseini 的既往成果与信誉中高深厚技术传承和顶级招聘能降低关键人集中度,但不能消除它索取接班梯队、下放后的技术所有权,以及创始人以下的组织架构图。
EDA + ML + 验证人才获取专业工程人才供给紧缺,既有厂商和超大规模云厂商也在招聘同类画像Ricursive 的品牌和资金有利于招聘,但人才市场仍紧复核验证、物理设计和基础设施岗位的招聘漏斗、录用接受率和填补周期。
运营与商业化搭建招聘信息明确覆盖运营类职能,说明非研究组织仍在搭建中中高中高新资金能支持团队搭建,但执行面仍在成形索取 GTM 领导梯队、客户成功计划和合规责任图。
设计栈全链条的工作流归属纪律要支撑全栈主张,公司必须协调的不只是一个点状 AI 工具,同时还要守住严谨性强创始人与强投资人有帮助,但责任归属必须能在多个项目中重复落地要求提供试点复盘,展示 Ricursive 如何处理交接、验证和客户变更管理。

人员风险偏高,因为 Ricursive 必须把研究卓越性与流程、安全、企业级执行结合起来,而且速度要快过大多数前沿实验室。

[CR001, CR002, CR007, CR036, CR038, CR041]
缓释与否决标准表
风险可监测触发项阈值 / 事件行动含义
商业验证缺口具名付费生产合作伙伴证据下一轮融资或重大估值事件到来时,仍没有具名设计定点、基准包或部署参考将 Ricursive 重新按研究资产承销,而不是按已被商业验证的平台承销。
验证 / 可靠性风险签核级基准披露管理层无法说明 Ricursive 在哪里优于或安全增强既有流程,以及哪些结果仍由人工验证负责下调转化假设,并把全栈自动化主张视为未验证。
出口管制暴露管线或支持工作流触发 D:5 / 澳门筛查复杂性有意义的账户活动依赖需要许可或特殊控制的实体或远程用户,而 Ricursive 无法拿出证据要求建立正式出口管制架构后,才支持进一步全球扩张。
既有厂商替代压力买方选择既有厂商 AI 流程,而不是 Ricursive在可比工作流中反复输给 Synopsys、Cadence 或 Siemens 扩展模块实质下调 TAM 和定价权假设。
计算烧钱与跑道基础设施扩张跑在认证进展前面紧急融资、可见支出激增,或基础设施扩张后仍没有从烧钱走向收入的可信桥梁提高要求回报,并缩短在验证前继续出资的容忍期。
执行面创始人离开,或验证 / 商业领导岗位招聘停滞关键技术或运营岗位持续空缺,或创始人减少主动经营角色暂停推进,直到领导层厚度和流程归属明确扩大。

这些否决标准由事件触发、可外部监测;它们聚焦会改变承销判断的信号,而不是泛泛的创业公司不确定性。

[CR006, CR008, CR012, CR022, CR027, CR030]

7.5 证据

Chapter 08

08估值

8.1 融资背景、稀释测算,以及为什么 $4B 标记需要纪律

Ricursive 在不到两个月内,从 2025 年 12 月约 $750 million 的种子轮估值跳到 2026 年 1 月 $4 billion 投后 Series A。 这样的跃升在当前前沿 AI 市场中并非不可能,但对一家尚未公开披露收入、ARR、毛利率、客户数或具名付费设计项目的公司来说, 仍是一次激进重估。现有证据支持的是一轮“创始人 + 可选性”融资:Anna Goldie 和 Azalia Mirhoseini 具备稀缺的 AlphaChip 与 TPU 可信度, 公司瞄准真实的设计瓶颈,顶级投资人也迅速围绕故事组成银团。融资数学同样重要。$4 billion 投后估值下的 $300 million 一级融资, 意味着约 $3.7 billion 投前估值,新增资金稀释仅约 7.5%;也就是说,这轮融资抬高参考价格的程度远大于改变股权基础。 公开证据支持存在一轮稀缺资产的市场出清融资;但在出现新里程碑前,还不足以支持以高于该轮的价格买入。 由于公开条款未披露清算优先权或治理保护,头条估值应被视为入场纪律的上限,而不是内在价值。[CV001, CV002, CV003, CV004, CV005, CV006]

建议摘要表
维度评估决策含义
建议跟踪 / 继续研究在商业验证改善前,不要承销一个干净的买入案。
信心创始人与市场质量很强,但变现证据仍薄。
风险评级执行、商业化和价格支撑风险仍然很高。
估值立场偏高$4B 估值更多定价的是未来成功,而不是已披露的当前表现。
目标回报纪律目前标价尚难支撑超过 2x 的总回报案大概率需要更低有效入场价、条款保护或异常亮眼的新里程碑。
当前锚点2026 年 1 月投后 $4B 的 Series A将上一轮作为入场纪律上限,而不是已证明的内在价值。
上调触发项具名付费客户,加上基准化设计定点会提高对价格由真实需求支撑、而不只是由稀缺性支撑的信心。
主要下行触发项到下一轮融资时仍无收入证明,或基准数据偏弱会提高叙事压缩或后续平轮 / 下轮融资的概率。

建议明确对价格和证据敏感;它不是对创始人质量的泛泛判断。

[CV001, CV024, CV025, CV040, CV045, CV049]
融资 / 估值背景表
维度当前公开证据入场纪律含义
种子轮锚点Dec 2025 种子轮:$35M,估值约 $750M判断 Series A 价格,要把不到两个月内 5.3x 的估值跳升纳入基准。
Series A 头条融资Jan 2026 轮:$300M,投后估值 $4.0B这是当前市场出清价格,但叙事权重仍然很高。
隐含投前估值 / 稀释投前约 $3.7B,新钱稀释约 7.5%这一轮重置了价格预期,但对降低业务风险的贡献小得多。
已披露累计融资种子轮和 Series A 合计融资 $335M资金足够招聘和搭建算力,但不足以构成公开变现证明。
公开经营支撑未公开披露收入、ARR、毛利率、客户数或定价仅凭公开证据,不应按高于上一轮的价格入场。
优先权 / 治理悬置风险优先权、董事会权利、反稀释棘轮条款和附函均未公开披露名义估值可能高估普通股的经济吸引力。
建议入场纪律只有客户、基准测试和股权结构表尽调通过后,才重新做 $4B 或以上的投资测算。若没有这些里程碑,把上一轮价格当作观察线,而不是追价依据。

用头条融资数学和披露缺口,把上一轮价格转成可执行的入场纪律框架。

[CV001, CV002, CV003, CV024, CV026, CV027]
FV001: 推荐逻辑

从创始人稀缺性和市场需求推导至当前「跟踪 / 继续研究」建议的决策链。

该流程是分析框架,不是机械公式;它把主要估值驱动因素压缩成一条可提交 IC 的推荐路径。

[CV005, CV015, CV024, CV025, CV036, CV045]

8.2 投资论点、反面论点和可比公司测算

正面承保逻辑很直接。芯片设计慢、贵,而且是 AI 基础设施的真实瓶颈;超大规模云厂商和模型公司仍在投资定制硅; Ricursive 的创始人所做 AlphaChip 工作已经影响多代 Google TPU。反面逻辑同样重要。公开客户证据仍然缺席, 公开财务披露很少,而既有 EDA 供应商已经在商业化 AI 辅助设计工作流,承诺更好的 PPA 结果和 5x-10x 生产率提升。 2026 年 7 月公开可比公司快照显示,Synopsys 收入倍数约 10.5x,Cadence 约 18.6x,NVIDIA 约 21.9x, AMD 约 24.4x。这些高倍数属于已经披露收入、拥有深厚安装基础和成熟商业化体系的公司。 从这些参照倒推,可以看出 Ricursive 需要多少运营实质,$4 billion 价格才会显得耐久,而不只是赶风口。 正确解读是,Ricursive 拥有高质量市场和产品论点,但客户与财务证据仍不足以穿透反面论点。[CV011, CV012, CV013, CV014, CV015, CV018]

正反论点表
维度多头论点反方论点什么会改变判断
市场需求AI 实验室和超大规模云厂商确实需要更快的定制硅迭代。真实瓶颈并不保证 Ricursive 能拿到有吸引力的经济性。多个付费项目,以及跨不止一个买方的扩张证据。
产品承诺AlphaChip 背景和递归式 AI-硬件协同设计支撑了有意义的产品论点。公开证据仍未显示其在生产中可重复地优于既有 EDA 工作流。关于设计周期、验证吞吐和 PPA 的独立基准数据。
客户验证主动找上门的战略兴趣说明买方确实好奇。战略兴趣不等于付费部署或续约行为。具名付费客户,以及生产或续约证据。
财务支持大额资本基础能支持人才和计算扩建。目前还没有公开收入、ARR、毛利率或定价披露来支撑估值。收入衔接路径、定价模型和利润率披露。
竞争Ricursive 可能成为芯片制造商和云实验室的战略赋能层。Synopsys 和 Cadence 已经把 AI 辅助自动化交付进客户工作流。Ricursive 在重要设计上显著优于既有基线的证据。
政策与技术风险创始人信誉和计算需求能继续吸引投资人注意力。AlphaChip 式优越性仍有争议,出口管制摩擦也可能拖慢商业化。第三方技术验证,加上政策约束可管理的证据。
退出逻辑稀缺性可能支撑又一轮溢价私募融资或合作。若没有披露支撑,近期 IPO 逻辑偏弱;当前估值已经吃掉了大部分上行叙事。数据室级别披露;回报相对上一轮还要多出低双位数百分点的风险溢价。

反向逻辑聚焦估值支撑和商业化证据,而不是否认 AI 芯片设计自动化的重要性。

[CV005, CV014, CV015, CV016, CV024, CV025]
可比估值表
可比对象状态 / 日期价值 / 指标隐含收入倍数或估值标记相关性局限
Ricursive 种子轮未上市 / Dec 2025$750M 估值;$35M 种子轮早期基础估值标记显示 January 2026 轮在短时间内跳升了多远。种子轮估值没有配套披露公开经营指标。
Ricursive Series A未上市 / Jan 2026$4.0B 投后估值;$300M 轮次最新私募市场出清价格当前入场纪律的主要锚点。仍缺公开收入、利润率或客户披露。
Synopsys上市 / Jul 2026$83.70B 市值;$8.00B TTM 收入~10.5x 市值 / 收入与 AI 芯片设计相关的直接 EDA 可比公司。规模大、成熟、业务多元的上市公司。
Cadence上市 / Jul 2026$102.91B 市值;$5.52B TTM 收入~18.6x 市值 / 收入最接近的上市 AI-EDA 工作流可比组。同样成熟、全球化,且已经商业化。
NVIDIA上市 / Jul 2026$4.718T 市值;$215.93B TTM 收入~21.9x 市值 / 收入AI 基础设施稀缺性的上限代理。硬件平台龙头,不是初创设计自动化可比对象。
AMD上市 / Jul 2026$844.35B 市值;$34.63B TTM 收入~24.4x 市值 / 收入fabless 模式下另一类 AI 芯片稀缺性代理。体量远大,披露也远多于 Ricursive。
Unconventional AI未上市 / Dec 2025$4.5B 估值;$475M 种子轮前沿 AI 稀缺性的叙事同行显示当前市场存在高于 Ricursive 的账面估值。不是直接的芯片设计自动化可比对象。
Rebellions未上市 / Mar 2026~$2.34B 估值;$400M pre-IPO 轮后期 AI 芯片参考显示一家融资到位的半导体公司有更明确的商业化意图。硬件供应商,而非设计工具平台。
XCENA未上市 / May 2026$570M 估值;$135M Series B低区间 AI 基础设施参考显示范围更具体的瓶颈型公司如何定价。以存储为中心的架构公司,不是芯片设计自动化。
Inferact未上市 / Jan 2026$800M 估值;$150M 种子轮AI 基础设施软件参考显示推理工具在没有上市公司级披露时仍能拿到强定价。推理软件不是半导体设计自动化。
MatX未上市 / Feb 2026$500M Series B;估值未披露融资里程碑参考印证投资人对 AI 算力挑战者的强需求。未披露估值,因此只能说明偏好,不能支撑价格。
Cognichip未上市 / Apr 2026$60M 融资;估值未披露芯片设计 AI 的直接邻近对象在公开初创公司报道中,与 Ricursive 的叙事最接近。阶段太早、披露太少,无法验证 Ricursive 定价。

上市公司收入代理使用市值和 TTM 收入快照。未上市初创行是估值参考点,不是基于倍数的可比公司。

[CV001, CV002, CV018, CV019, CV020, CV021]
FV002: 估值敏感性

在选定上市公司收入倍数视角下,Ricursive 若要支撑 $4B 估值所需的隐含年收入。

数值只是用 $4,000M 除以所选倍数得到的简单隐含收入结果,不是 Ricursive 管理层指引。

[CV018, CV019, CV020, CV021, CV022, CV023]

8.3 情景框架、下行触发因素和回报测算

不利情形并不是 Ricursive 缺乏技术人才,而是估值可能跑在可复现商业差异化前面。New Scientist 记录了专家质疑: AlphaChip 式主张是否已经公开证明能持续优于专家设计师或商业工具;与此同时,Synopsys 和 Cadence 已经把生产级 AI 优化产品卖进真实客户工作流。 这给 Ricursive 设下很高门槛:公司不仅要证明 AI 能帮芯片设计,还要证明自己的具体系统能创造足够可衡量的速度、验证或 PPA 优势, 从而把预算从既有供应商手里拉走,或作为赋能层叠在它们之上。熊市情形因此围绕执行错配:精英创始人、重算力和招聘投入, 但付费部署或有基准的结果转化缓慢。基准情形让估值维持在当前水平附近,因为稀缺 AI 基础设施故事仍能吸引充裕资本。 牛市情形要求具名客户、有基准的设计胜利,以及公司能从 $4 billion 入场价复合到至少可信的 1.5x-2.0x 总价值扩张, 而不只是守住上一轮估值的证据。[CV007, CV008, CV009, CV010, CV014, CV015]

乐观 / 基准 / 悲观情景表
情景概率信号估值区间相对当前 $4B 的毛 MOIC关键假设主要失败模式
悲观30%$2.5B-$3.25B0.6x-0.8xRicursive 吸引了关注,但经基准验证或付费牵引不足,撑不起 January 2026 溢价。下一轮融资需要围绕证据重新定价,而不是围绕稀缺性。
基准50%$3.75B-$4.75B0.9x-1.2x公司把投资人热情转成早期项目,但仍缺完整经营披露。商业证明落地慢于招聘和算力开支爬坡。
乐观20%$6.0B-$8.0B1.5x-2.0xRicursive 在重要客户项目中证明可衡量的设计周期压缩和 PPA 提升,并获得战略稀缺性溢价。在 Ricursive 放大收入前,既有厂商追平功能集。
概率加权中枢100%~$4.0B-$4.2B~1.0x只有未来 12-18 个月基准情景开始兑现,当前轮次价格才大致站得住。若没有里程碑,估值加权中枢会滑到上一轮标记以下。

区间是分析师情景框架,不是公司指引;由于 Ricursive 尚未披露收入或利润率输入,框架保留不确定性。

[CV037, CV038, CV039, CV043, CV044, CV045]
投资逻辑破裂与止损触发因素表
触发因素阈值 / 事件对投资逻辑的传导行动含义
相对既有厂商的基准差距在客户相关设计上,相比 Synopsys/Cadence 工作流没有清晰提升削弱核心主张:Ricursive 是差异化平台,而不只是光环项目。把估值立场推向悲观情景,并要求显著更低的入场价格。
没有具名付费客户下一轮融资仍没有客户名称、付费试点或收入区间说明商业证明落后于资本投放。建议维持在继续研究或更低。
技术质疑延续第三方复现仍未显示清晰的 AlphaChip 式优势提高叙事跑在可复现优势前面的概率。把公司视为实验性基础设施 R&D,而不是规模化软件平台。
政策摩擦升高出口管制或生态规则限制跨境 AI 芯片项目可能放慢获客,并收窄伙伴集合。提高所需安全边际,并缩短投资测算周期。
条款悬置风险浮现Series A 优先权、反稀释棘轮条款或治理权利显著压低普通股上行空间可能让名义 $4B 估值在经济上不那么有吸引力。任何承诺前,先基于股权结构表重建回报测算。

每个触发因素都可能改变概率加权估值走廊,或改变按当前估值买入的经济吸引力,因此被纳入。

[CV017, CV033, CV036, CV037, CV040, CV045]
FV003: 估值 / 回报区间

基于证据质量和执行里程碑,为 Ricursive 估算悲观、基准和乐观估值区间(以十亿美元计)。

情景区间是分析师估算,既保留不确定性,也围绕最新融资估值锚定。

[CV037, CV038, CV039, CV043, CV044, CV045]

8.4 建议、退出准备度和最终尽调要求

今天最可辩护的判断仍是跟踪 / 继续研究:中等置信度、高风险、估值偏紧。Ricursive 如果能展示更快设计周期、 更好算力效率,以及在重大芯片项目中的可重复客户采用,就可能具备战略重要性。但公开材料仍缺少把一家有吸引力的公司转化为明确投资入口所需的承保输入: 收入形态、具名付费客户、毛利结构、对比既有工作流的基准证据,以及 Series A 中嵌入的经济权利。 这很关键,因为从当前估值出发,情景集并不明显能给出经典 VC 回报。即使建模的牛市情形, 在任何稀释或优先权影响之前,也只达到从 $4 billion 出发约 1.5x-2.0x 总 MOIC。 因此,短期更好的路径是等待结构化下一轮、战略合作,或由里程碑驱动的重新定价,而不是追逐头条估值。 买方只有在 Ricursive 能说明谁在付费、交付了什么可衡量改善,以及股权表是否给普通股上行留下足够空间之后,才应提高确信度。[CV023, CV024, CV025, CV032, CV038, CV039]

最终尽调问题表
主题缺失证据重要性尽调路径
收入模型当前收入、软件 / 许可 / 服务属性,以及任何 ARR 口径没有收入形态,上市可比只能做代理测算。索取收入桥、定价模型,以及确认收入与签约收入明细。
客户证明具名付费客户、项目规模、生产与试点状态、续约路径估值故事必须从战略兴趣转成已变现采用。询问头部设计伙伴、合同阶段和用例结果。
基准测试结果相对既有工作流的实测布局时间、验证吞吐和 PPA 提升技术转商业的核心证明就在这里。索取第三方基准测试包和客户背调对象。
毛利率和算力成本训练 / 推理单元经济、服务收入占比和交付模型如果算力或服务拖累利润率,软件式倍数就难以成立。审查队列级毛利率和算力 COGS 假设。
Series A 条款优先股堆叠、董事会权利、pro rata 结构和任何投资人保护经济吸引力可能与名义估值显著不同。获取股权结构表、股票购买协议和主要投资人附函。
现金跑道和招聘计划烧钱速度、招聘速度和算力 capex 承诺有助判断当前轮融资是在资助证明,还是只是延长实验。索取经营计划、烧钱桥和算力基础设施承诺。

买方若要在 January 2026 投后基准之上做有意义的投资测算,至少要完成这些尽调事项。

[CV024, CV029, CV031, CV032, CV045, CV047]
退出就绪度表
路径就绪度支撑因素阻碍因素视角变化条件
下一轮私募融资顶级投资人组合和创始人稀缺性仍能吸引资本。若下一轮仍没有客户或基准证明,估值压缩风险会上升。展示付费牵引,并控制烧钱速度。
战略合作 / 渠道交易中高目标客户包括大型芯片制造商和云实验室,战略兴趣可见。这些兴趣尚未以经常性收入或生产部署形式披露。公布有意义的设计 win 或嵌入式工作流集成。
战略出售中低大型 EDA、算力或超大规模云厂商可能看重人才和工作流 IP。买家仍会要求差异化可持续、可集成的证据。证明一项既有厂商无法低成本复制的必备能力。
IPO / 上市路径披露质量足够强时,市场会奖励 AI 基础设施稀缺性。Ricursive 缺少公开收入、利润率、客户和监管文件级透明度。建立 IPO 级披露、收入规模和治理可见度。

就绪度仅按公开证据判断;私下尽调可能显著改善或恶化每条路径。

[CV035, CV046, CV048, CV049, CV050]
FV004: 投资 KPI

一张 IC 风格评分卡,覆盖最能决定 Ricursive 能否不止靠叙事撑估值的维度。

分数是基于来源证据的分析判断,不是公司披露,也不是管理层给出的量化评级。

[CV014, CV024, CV025, CV031, CV036, CV045]

免责声明

本报告仅供信息参考,不构成投资建议。

证据索引

结论
编号陈述可信度来源
CO001 Public sources consistently refer to the target company as Ricursive Intelligence even though this report run was requested as Recursive Intelligence. SO001, SO014, SO017
CO002 The official homepage title itself misspells the brand as Riculsive Intelligence while the body copy says Ricursive Intelligence. SO001
CO003 Ricursive describes itself as a frontier AI lab building self-improving systems starting with chip design. SO001, SO011, SO017
CO004 TechCrunch reported that Ricursive is building AI tools that design chips rather than manufacturing chips itself. SO015
CO005 Independent coverage places Ricursive in Palo Alto, California. SO018, SO023, SO025
CO006 The public Ashby jobs board and role listings place Ricursive’s visible hiring footprint on-site in Palo Alto. SO003, SO004, SO005, SO006, SO007, SO008, SO009, SO010
CO007 Ricursive publicly launched in early December 2025 with a $35 million seed round at a $750 million valuation. SO017, SO014, SO023
CO008 By the run date Ricursive remained a private company but had progressed from launch to post-Series A stage. SO014, SO016
CO009 Anna Goldie is publicly identified as Ricursive’s co-founder and CEO. SO015, SO017
CO010 Azalia Mirhoseini is publicly identified as Ricursive’s co-founder and CTO. SO015, SO017
CO011 TechCrunch said Goldie and Mirhoseini worked together at Google Brain, Anthropic, and Google again before founding Ricursive. SO015
CO012 Sequoia, TechCrunch, and DeepMind all connect Goldie and Mirhoseini to the creation of AlphaChip. SO013, SO015, SO021
CO013 DeepMind said AlphaChip was used in hardware around the world, and Ricursive-linked sources say the approach informed four generations of Google TPU. SO021, SO013, SO016
CO014 Sequoia’s January 2026 podcast framed Ricursive’s mission as enabling a move from fabless to designless custom silicon. SO013
CO015 Lightspeed led a $300 million Series A at a $4 billion post-money valuation on January 26, 2026. SO014, SO016, SO018
CO016 Public reporting converges on $335 million of total capital raised after adding the $35 million seed to the $300 million Series A. SO014, SO015, SO023
CO017 The official Series A announcement named DST Global, NVentures, Felicis Ventures, 49 Palms Ventures, Radical AI, and Sequoia Capital as participants. SO016, SO014
CO018 Sequoia Capital led the seed round that accompanied Ricursive’s launch. SO017, SO014, SO023
CO019 Ricursive’s homepage summarizes the backer set as Sequoia, Lightspeed, DST, and NVentures. SO001, SO016
CO020 The seed and Series A proceeds were publicly earmarked for scaling the research and engineering team and compute infrastructure. SO016, SO017
CO021 Lightspeed’s investment note says chip design often takes two to three years and hundreds of millions of dollars, and Ricursive aims to compress that cycle to weeks. SO012, SO023
CO022 TechCrunch reported that Nvidia is an investor while Nvidia, AMD, Intel, and other chip makers are target customers for Ricursive’s tools. SO015, SO022
CO023 Ricursive’s homepage says the team has hands-on experience developing Gemini, Claude, Grok, and TPUs. SO001
CO024 Official materials say Ricursive has attracted talent from Google DeepMind, Anthropic, NVIDIA, Cadence, Apple, xAI, Stanford, MIT, and Harvard. SO001, SO016
CO025 The careers page says Ricursive is scaling a small, elite team across AI, engineering, technical, and operational disciplines. SO001, SO002
CO026 The Ashby board listed seven full-time on-site openings spanning EDA, LLM infrastructure, software infrastructure, RTL verification, security, research, and general hiring. SO003, SO004, SO005, SO006, SO007, SO008, SO009, SO010
CO027 The EDA Algorithm Engineer posting shows Ricursive is hiring directly into chip-design automation rather than only model research. SO003, SO008
CO028 The RTL and Design Verification Engineer posting shows the company is building verification depth alongside AI research. SO003, SO006
CO029 The Founding Security Engineer posting shows the operating stack requires early security ownership rather than a research-only staffing model. SO003, SO010
CO030 The LLM Infra and SWE Infrastructure postings show Ricursive is investing in model systems and internal tooling as well as chip-design algorithms. SO003, SO007, SO009
CO031 The reviewed public corpus did not disclose revenue, ARR, or a commercial customer count for Ricursive. SO001, SO014, SO015, SO016, SO018, SO020
CO032 The reviewed public corpus did not disclose total employee headcount, so hiring activity is only a proxy for scale. SO001, SO002, SO003, SO025
CO033 Adverse and neutral coverage alike framed the $4 billion round around founder pedigree and infrastructure thesis rather than disclosed commercial revenue or a shipped chip product. SO014, SO015, SO020
CO034 TechCrunch and other coverage emphasized that Ricursive reached its Series A less than two months after public launch. SO014, SO018, SO023
CO035 Sequoia’s podcast says companies spending more than $100 billion on AI inference could benefit from custom silicon without maintaining hundreds or thousands of chip designers. SO013
CO036 Lightspeed said AlphaChip was adopted by MediaTek outside Google, showing the founders’ pre-Ricursive work already reached external semiconductor firms. SO012, SO021
CO037 Business 2.0 and Lightspeed’s note both describe Ricursive’s goal as compressing chip-design cycles from multi-year timelines to weeks. SO012, SO023
CO038 Reviewed public sources did not disclose a board roster, independent directors, or concrete investor governance rights beyond named financing participants. SO001, SO013, SO016, SO017, SO018
CO039 Reviewed public sources did not name signed commercial partnerships or reference customers, leaving go-to-market validation incomplete. SO001, SO015, SO016, SO017, SO020
CO040 Reviewed public web sources did not surface regulatory, litigation, or enforcement events tied to Ricursive as of the run date, but that absence is only a low-confidence web-scan result. SO014, SO015, SO018, SO020
CO041 Silicon Valley Daily’s headline used “$400 million Series A” even though the company’s official round size was $300 million, underscoring secondary-reporting noise. SO024, SO016
CO042 Across the homepage and major coverage, Ricursive is consistently presented as an AI-for-chip-design platform rather than as a direct GPU or chip manufacturer. SO001, SO015, SO018
CO043 TechCrunch explicitly warned readers not to confuse Ricursive Intelligence with Richard Socher’s similarly named startup Recursive. SO014
CM001 Ricursive is positioning itself as an AI company for semiconductor design rather than as a chip manufacturer or foundry. SM001, SM002, SM003
CM002 Ricursive says its product ambition is a full-stack chip-design platform that starts with layout and extends across the broader design workflow. SM001, SM003, SM005
CM003 TechCrunch reports that Ricursive intends to handle everything from component placement through design verification. SM003
CM004 Ricursive and its backers frame the company as an enabler of custom-silicon creation rather than as a seller of finished AI accelerators. SM001, SM002, SM005
CM005 Synopsys DSO.ai and Cadence Cerebrus show that AI-assisted chip-design automation is already a commercial software category inside broader EDA workflows. SM007, SM008, SM009
CM006 Synopsys DSO.ai is positioned as an autonomous AI application for chip design that uses reinforcement learning to search very large solution spaces for power, performance, and area optimization. SM007, SM008
CM007 Cadence Cerebrus is positioned as an AI-driven automated chip-design flow optimizer that uses full-flow reinforcement learning and LLM capabilities to improve PPA and engineering productivity. SM009, SM010
CM008 Nature describes chip floorplanning as an engineering task that historically required months of intense effort by physical-design engineers. SM011
CM009 Nature reports that its reinforcement-learning method generated floorplans in under six hours that were superior or comparable to human output on the reported designs. SM011
CM010 New Scientist reports that independent researchers say public evidence still does not prove AlphaChip outperforms expert humans or commercial software on current benchmark designs. SM012
CM011 Lightspeed says the most performant silicon still takes large teams two to three years and hundreds of millions of dollars to design. SM005
CM012 AWS says Synopsys DSO.ai can identify design optimizations in weeks rather than months by exploring large design spaces automatically. SM008
CM013 AWS gives concrete DSO.ai examples including 20 percent better leakage power and smaller-area outcomes on specific workloads. SM008
CM014 Forbes says semiconductor AI tooling has already delivered roughly 10x productivity gains on relatively narrow tasks such as floor-plan optimization. SM010
CM015 Ricursive targets companies that make electronics and need chips, which puts fabless chipmakers, systems companies with custom ASIC roadmaps, and hyperscaler silicon teams inside its buyer universe. SM003, SM002, SM023
CM016 AWS markets Trainium as a purpose-built AI chip for high-performance training and inference at scale. SM013
CM017 Google says TPUs are custom-designed accelerators used for Gemini and other Google AI applications. SM014
CM018 Microsoft says Maia 200 is its inference accelerator built on TSMC 3nm and delivers 30 percent better performance per dollar than the latest generation hardware already in its fleet. SM015
CM019 The presence of Trainium, TPU, and Maia shows that hyperscalers are now sustaining a real custom-silicon race rather than treating AI chips as a one-off experiment. SM013, SM014, SM015
CM020 SEMI says front-end fab-equipment spending should reach 110 billion dollars in 2025 and 130 billion dollars in 2026 as AI-related chip demand drives capacity expansion. SM016
CM021 That SEMI fab-equipment forecast is an adjacent downstream capex signal rather than Ricursive’s addressable software market. SM016, SM001, SM003
CM022 Synopsys generated about 8.00 billion dollars of revenue in 2025 and Cadence generated about 5.29 billion dollars in 2025, creating an observable 13.29 billion dollar upper-bound proxy for the broad EDA and IP software pool. SM019, SM020
CM023 The same combined revenue pool is about 13.52 billion dollars on a 2026 trailing-twelve-month basis, suggesting the broad EDA software ceiling is growing but still far below semiconductor capex or AI-compute revenue pools. SM019, SM020, SM016
CM024 Cadence and Synopsys together were worth roughly 193.08 billion dollars in public market capitalization in June 2026, which is useful valuation context but not a spend-based TAM measure. SM021, SM022
CM025 The monetized AI chip-design automation segment is narrower than the broad EDA pool because public category proof today centers on PPA, floorplanning, and flow optimization rather than total workflow replacement. SM007, SM008, SM009, SM011
CM026 A conservative near-term annual spend range for AI chip-design automation is about 0.5 to 1.5 billion dollars if adoption remains concentrated in point-tool workflows such as floorplanning and PPA optimization. SM007, SM008, SM009, SM011
CM027 A base-case near-term SAM of roughly 2.0 to 5.0 billion dollars is plausible only if advanced custom-silicon teams adopt automation across multiple stages from placement into verification and signoff. SM003, SM005, SM007, SM009
CM028 The broad 13-plus-billion-dollar incumbent revenue pool is best treated as Ricursive’s outer ceiling rather than as its realistic near-term SAM because it already includes legacy tools, IP, and workflows Ricursive has not yet displaced. SM019, SM020, SM003, SM005
CM029 The status-quo substitute for Ricursive is a labor-heavy incumbent EDA flow where engineering teams iterate manually inside established tools until they reach design closure. SM005, SM008, SM009
CM030 The closest adjacent substitutes are incumbent AI modules from Synopsys and Cadence rather than foundries, fab-equipment vendors, or AI-chip manufacturers. SM007, SM008, SM009, SM016
CM031 The most likely initial budget owners are CAD, physical-design, or silicon-platform leaders, with economic sponsorship escalating to vice presidents of engineering or silicon when the platform touches multiple workflow stages. SM003, SM008, SM009
CM032 The natural adoption path is to win a benchmark or pilot on one block, then expand into signoff, verification, and broader program deployment after engineers trust the results. SM003, SM008, SM009, SM010
CM033 The strongest growth driver is the custom-silicon arms race, because hyperscalers and advanced chip teams gain disproportionate value from shortening a design cycle that currently lasts years. SM005, SM013, SM014, SM015
CM034 A second growth driver is that incumbent tools have already normalized the idea that AI can improve chip-design productivity and PPA. SM007, SM008, SM009, SM010
CM035 The main adoption constraints are flow-integration risk, switching cost into entrenched EDA stacks, and customer trust about whether automation generalizes beyond narrow tasks. SM008, SM009, SM010, SM012
CM036 Ricursive has not publicly disclosed named production design wins, public pricing, or verification benchmarks, so valuation still depends more on founder pedigree and category promise than on demonstrated market penetration. SM003, SM004, SM023, SM024, SM025
CM037 BIS and Morrison Foerster indicate that advanced-semiconductor export controls now create real enforcement and customer-mix risk across the AI-chip ecosystem. SM017, SM018
CM038 Ricursive therefore belongs inside a narrow but high-value AI chip-design automation layer within EDA, not inside the much larger buckets of semiconductor manufacturing spend, fab equipment, or AI-chip revenue. SM001, SM003, SM016, SM020
CM039 The most defensible three-layer sizing logic is a broad 13.29 to 13.52 billion dollar incumbent-software ceiling, a narrower 2.0 to 5.0 billion dollar multi-stage automation SAM, and a 0.5 to 1.5 billion dollar near-term point-tool beachhead. SM019, SM020, SM007, SM009
CM040 The buyer journey runs from technical benchmark credibility to pilot deployment to workflow standardization, which means Ricursive’s commercial timing is gated by proof, not just by TAM rhetoric. SM003, SM008, SM009, SM012
CP001 Recursive Intelligence, publicly branded Ricursive Intelligence, describes itself as a frontier AI lab building self-improving systems that start with chip design. SP001, SP029
CP002 Recursive's launch and Series A materials frame the product as a platform meant to accelerate and optimize semiconductor design while closing the loop between AI and the hardware that fuels it. SP002, SP029
CP003 Lightspeed says the most performant silicon typically takes large teams two to three years and hundreds of millions of dollars to design. SP003
CP004 TechCrunch and Data Center Dynamics both describe Recursive as building AI tools that design chips rather than manufacturing the chips themselves. SP004, SP027
CP005 Synopsys positions DSO.ai as autonomous RTL-to-GDSII full-flow optimization that reduces design time and improves design quality across logical and physical domains. SP005, SP007
CP006 AWS says DSO.ai on AWS uses reinforcement learning to improve power, performance, and area while identifying optimization opportunities in weeks rather than months. SP007, SP005
CP007 Synopsys's 2026 chip-design blog shows the incumbent roadmap has already moved from point optimization toward generative and agentic AI for engineering productivity. SP006, SP005
CP008 Cadence describes Cerebrus as an AI-driven automated approach to chip-design flow optimization that improves PPA and productivity. SP008, SP019
CP009 Cadence says the 2026 ChipStack AI Super Agent autonomously creates and verifies designs from specifications and high-level descriptions with up to 10x productivity improvement. SP009, SP008
CP010 Siemens says Solido offers AI-enabled variation-aware design, IP validation, library characterization, and simulation used by thousands of designers at top semiconductor companies worldwide. SP010
CP011 Embedded.com says agentic AI is entering EDA engineering workflows because rising SoC complexity is driving exponential growth in engineering hours. SP011
CP012 As of July 2026 Synopsys had a public market-cap proxy of about $83.70 billion and TTM revenue of about $8.00 billion. SP032, SP033
CP013 As of July 2026 Cadence had a public market-cap proxy of about $102.91 billion and TTM revenue of about $5.52 billion. SP034, SP035
CP014 Synopsys and Cadence therefore enter AI-assisted chip design from multibillion-dollar installed bases and enterprise procurement relationships that Recursive does not yet show publicly. SP018, SP019, SP032, SP034, SP001
CP015 DeepMind says AlphaChip can generate superhuman or comparable chip layouts in hours rather than weeks or months and that its layouts are used in hardware around the world. SP012
CP016 New Scientist reports that independent experts dispute whether public evidence proves AlphaChip outperforms expert human designers or commercial tools. SP013
CP017 Google Research's circuit_training repository is an open-source framework for generating chip floorplans with distributed deep reinforcement learning that reproduces the AlphaChip methodology. SP014
CP018 Because the floorplanning lineage is open-source, sophisticated internal teams can reproduce part of the AlphaChip method without buying Recursive software. SP012, SP014
CP019 Google says TPUs are custom-designed accelerators purpose-built for AI workloads. SP015
CP020 AWS says Trainium is a purpose-built AI chip designed to deliver the best economics for AI training and inference at scale. SP016
CP021 Microsoft says Maia 200 improves the economics of AI inference and claims FP4 and FP8 performance advantages versus Trainium, TPU, and Microsoft's own prior fleet hardware. SP017
CP022 The public TPU, Trainium, and Maia pages show that major hyperscalers increasingly answer hardware bottlenecks by building first-party silicon and internal toolchains. SP015, SP016, SP017
CP023 As of July 2026 NVIDIA had a public market-cap proxy of about $4.718 trillion and TTM revenue of about $215.93 billion. SP036, SP037
CP024 As of July 2026 AMD had a public market-cap proxy of about $844.35 billion and TTM revenue of about $34.63 billion. SP038, SP039
CP025 For many enterprises, buying merchant accelerators from NVIDIA or AMD is a more immediate substitute than starting a custom-silicon program that would need Recursive-like tooling. SP003, SP036, SP038
CP026 Recursive's retained public materials do not disclose pricing, packaging, named customers, security attestations, or compliance certifications. SP001, SP002, SP004, SP029
CP027 Because Recursive pricing is undisclosed and incumbent EDA pricing is also not public in the retained set, public analysis can compare packaging logic but not contract economics. SP001, SP005, SP008, SP010
CP028 Recursive's sharpest public differentiation claim is broader self-improving automation ambition rather than a single point-optimization tool. SP001, SP002, SP029
CP029 Recursive says its team is behind AlphaChip, RL-CCD, Insta, and C3PO and has hands-on experience developing Gemini, Claude, Grok, and TPUs. SP001, SP029
CP030 AWS presents DSO.ai as deployable with AWS ParallelCluster, AWS Batch, multiple instance types, multiple job queues, and schedulers such as Slurm. SP007
CP031 Cadence's Cerebrus and ChipStack narratives keep designers inside the incumbent Cadence process and therefore lower switching friction for existing Cadence accounts. SP008, SP009
CP032 Siemens Solido broadens incumbent competition in custom-IC AI workflows even if it is less of a full digital signoff suite than Synopsys or Cadence. SP010, SP011
CP033 No retained public source names a Recursive customer, taped-out design win, or benchmark against DSO.ai, Cerebrus, ChipStack, or Solido. SP001, SP002, SP004, SP005, SP008, SP009, SP010
CP034 Public evidence still treats Recursive as pre-customer and pre-benchmark despite its large financing. SP002, SP004, SP027, SP028
CP035 TechCrunch says Cognichip raised $60 million in April 2026 to build deep-learning models that it claims can cut chip-development cost by more than 75% and timelines by more than half. SP022
CP036 MatX says its 2026 Series B backs MatX One, an LLM chip focused on higher throughput and lower latency rather than design-automation software. SP023
CP037 Rebellions says it raised $400 million in a pre-IPO round and launched vertically integrated AI infrastructure for production-scale inference environments. SP024, SP025, SP030
CP038 Crunchbase says semiconductor startups had absorbed about $10.7 billion of seed-to-pre-IPO funding by mid-2026. SP026
CP039 Crunchbase says global startup investment reached about $300 billion in Q1 2026, driven by unprecedented spending on AI compute and frontier labs. SP031
CP040 2026 entrant financings around Cognichip, MatX, and Rebellions show that buyer budgets and talent are being contested by adjacent silicon entrants before Recursive has public proof at scale. SP022, SP023, SP024, SP026, SP031
CP041 Recursive's direct commercial rivals are incumbent EDA suites Synopsys DSO.ai and Cadence Cerebrus or ChipStack, while Siemens is an adjacent incumbent and open-source AlphaChip, internal build, and merchant silicon compete as substitutes. SP005, SP008, SP009, SP010, SP014, SP015, SP016, SP017, SP036, SP038
CP042 The most likely commoditization path is AI capability becoming bundled into incumbent EDA platforms and private internal toolchains while many customers continue buying merchant accelerators instead of designing custom silicon. SP006, SP009, SP010, SP015, SP016, SP017, SP036, SP038
CP043 Competitive verdict: Recursive looks differentiated on founder pedigree, funding, and ambition, but disadvantaged on distribution, trust signals, public customer proof, and benchmark evidence. SP003, SP004, SP018, SP019, SP027
CP044 Data Center Dynamics and Crunchbase both describe Recursive as having raised $300 million at a $4 billion valuation within roughly two months of launch. SP027, SP028
CP045 TechCrunch explicitly places Recursive in the same 2026 mega-funding cohort as Unconventional AI, showing that valuation momentum alone does not validate competitive traction. SP004
CP046 Synopsys's investor overview describes the company as a valued silicon-to-systems design partner shaped by AI, silicon proliferation, and software-defined systems. SP018
CP047 Cadence's investor overview describes the company as a market leader in AI and digital twins serving leading semiconductor and systems companies. SP019
CP048 NVIDIA's investor home and AMD's investor site reinforce the scale and disclosure depth of merchant-silicon substitutes. SP020, SP021, SP036, SP038
CP049 Recursive's moat therefore has to come from workflow breadth, data feedback loops, and deployment execution rather than from macro-placement science alone. SP001, SP003, SP012, SP014
CP050 The AlphaChip critique raises the public proof burden on any startup claiming reinforcement-learning-driven chip-design superiority. SP012, SP013
CP051 EDA competition is diffusing beyond two vendors because Synopsys is pushing agentic AI, Cadence launched ChipStack, Siemens markets AI-enabled Solido, and industry observers now describe agentic AI as part of the engineering workflow. SP006, SP009, SP010, SP011
CP052 Recursive's best near-term wedge is a design team that wants broader automation than DSO.ai or Cerebrus but lacks hyperscaler-scale ability to build internally. SP001, SP003, SP015, SP016, SP017
CP053 Distribution and support power still sit with incumbents and hyperscaler ecosystems rather than with Recursive's current public footprint. SP007, SP018, SP019, SP020, SP021
CP054 No retained public source discloses public list pricing for Recursive, Synopsys DSO.ai, Cadence Cerebrus or ChipStack, or Siemens Solido. SP001, SP005, SP008, SP009, SP010
CP055 Open-source and internal-build paths are cheaper in software spend but far more demanding in specialist talent, compute, and organizational capacity than buying an external tool. SP003, SP014, SP015, SP016, SP017
CP056 Merchant hardware substitutes deliver the lowest workflow change because procurement can solve near-term AI capacity needs without adopting a new chip-design toolchain. SP020, SP021, SP036, SP038
CI001 Ricursive describes itself as a frontier AI lab building self-improving systems starting with chip design. SI001, SI003
CI002 Ricursive says it is closing the loop between AI and the hardware that fuels it. SI001
CI003 Ricursive publicly says it is backed by $335 million from Sequoia, Lightspeed, DST, and NVentures. SI001, SI007
CI004 Ricursive says it is scaling a small elite team and hiring across AI, engineering, technical, and operational disciplines. SI001, SI002
CI005 TechCrunch reported that Ricursive is building AI tools that design chips rather than chips themselves. SI005, SI006
CI006 TechCrunch reported that Ricursive targets Nvidia, AMD, Intel, and other chip makers as customers. SI006
CI007 TechCrunch reported that Ricursive intends its platform to handle work from component placement through design verification. SI006
CI008 TechCrunch reported that Ricursive will not publicly name early customers even though the founders say they can choose their first development partners. SI006
CI009 Ricursive said the Series A proceeds will scale its research and engineering team and significantly expand compute infrastructure. SI007
CI010 Ricursive said AlphaChip had been adopted across four TPU generations and deployed by external semiconductor companies. SI007
CI011 Lightspeed wrote that leading-edge silicon programs can take two to three years and hundreds of millions of dollars to design. SI003, SI004
CI012 Lightspeed wrote that EDA tooling contributes to chip-design cost but labor is the bulk of semiconductor research-and-development spend. SI003
CI013 Lightspeed wrote that expensive legacy EDA licenses and large design teams limit custom silicon to companies with scale. SI003
CI014 Lightspeed described Ricursive as building a full-stack platform to operationalize AI-enabled chip design at scale. SI003, SI007
CI015 Sequoia said Ricursive is pushing a shift from fabless to designless, where any company can create custom silicon through Ricursive. SI004
CI016 DeepMind said AlphaChip had reduced chip floorplanning from months to hours and was used in the last three TPU generations as of September 2024. SI011
CI017 The reviewed Ricursive public sources disclose fundraising and strategy but do not disclose revenue, ARR, or gross margin. SI001, SI005, SI006, SI007, SI010
CI018 The reviewed Ricursive public sources do not disclose list pricing, contract duration, or support tiers. SI001, SI005, SI006, SI007
CI019 The most supportable public revenue model is software platform licensing plus implementation or services rather than chip sales. SI003, SI005, SI006
CI020 Public GTM evidence points to a high-touch enterprise design-partner motion rather than self-serve distribution. SI004, SI006, SI007
CI021 Public sales-efficiency proxies are weak because no reviewed source discloses CAC, payback, pipeline conversion, or realized pricing. SI001, SI006, SI010
CI022 Synopsys' 2025 annual report shows $7,054.2 million of revenue and $1,623.5 million of cost of revenue, implying roughly 77% gross margin for a mature design-software and IP vendor. SI021
CI023 Synopsys says perpetual licenses are recognized upfront, support service revenue is recognized ratably, and professional services are recognized over time. SI021
CI024 Cadence' 2025 annual report says 91% of revenue came from product and maintenance and 9% came from services. SI020
CI025 Synopsys investor relations reports $7+ billion of annual revenue and 28,000+ employees. SI019
CI026 Official AI-EDA incumbents market productivity gains and workflow breadth rather than public list prices. SI014, SI016, SI018
CI027 Cadence says Cerebrus can accelerate chip delivery by 5X to 10X and let a single engineer design multiple blocks. SI016
CI028 Synopsys says DSO.ai reduces design time and compute costs through autonomous optimization. SI014
CI029 HCLTech says AI-era chip design economics increasingly depend on chiplets, advanced packaging, smarter physical design, and trusted toolchains rather than node shrinks alone. SI025
CI030 Siemens says 3D IC scaling creates tightly coupled thermal, mechanical, and electrical interactions that can propagate failures across dies. SI023
CI031 Siemens says HBM3 and HBM3E 3D-IC architectures increase design complexity through multi-chiplet planning, inter-die connectivity, and system-level modeling. SI024
CI032 Semiconductor Engineering's 2026 panel said AI will automate tedious design tasks but will not replace EDA tools or human oversight in the near term. SI022
CI033 The same 2026 panel said chip design is extremely expensive in time and money and that full automation still risks producing chips that do not work. SI022
CI034 CIOL argued that Ricursive's $4 billion valuation rests more on investor conviction than on publicly available benchmarks or products. SI010
CI035 CIOL argued that capital is flowing ahead of proof across self-improving AI hardware startups before they ship a single product. SI010
CI036 TechCrunch and Crunchbase reported that Ricursive moved from a $35 million seed at a $750 million valuation to a $300 million Series A at a $4 billion valuation in less than two months. SI006, SI008, SI009
CI037 Ricursive's public Series A investor roster included Lightspeed, DST Global, NVentures, Felicis, 49 Palms, Radical, and Sequoia. SI007, SI008
CI038 Public sources disclose total capital raised but do not disclose current cash on hand, monthly burn, runway, or debt obligations. SI001, SI007, SI010
CI039 Public financing is directed toward research talent and compute infrastructure rather than any disclosed manufacturing footprint or broad GTM buildout. SI002, SI003, SI007
CI040 No reviewed source discloses named current customers, customer count, backlog, or signed commercial benchmarks for Ricursive. SI001, SI006, SI010
CI041 Ricursive's public traction is founder pedigree, AlphaChip deployment history, investor roster, and interest from unnamed major chip makers rather than revenue or usage metrics. SI006, SI007, SI011, SI010
CI042 Relative to mature EDA analogs, Ricursive lacks filing-grade disclosure on revenue mix, margin, and services split. SI019, SI020, SI021, SI001, SI007
CI043 Ricursive's likely near-term cost structure is R&D-heavy and compute-intensive, with added service-delivery burden from implementation, verification, and human-in-the-loop design work. SI003, SI007, SI022, SI023, SI024
CI044 Mature EDA-like gross margins are possible only after Ricursive shifts from bespoke development work into repeatable software, IP, maintenance, and support contracts. SI020, SI021, SI022
CI045 Ricursive's next financing trigger is publicly undisclosed and most plausibly depends on productization speed, compute expansion, or slow commercial conversion. SI003, SI007, SI022
CI046 Ricursive is less capital intensive than a fab or cloud-infrastructure startup but still materially more capital intensive than ordinary software because compute and scarce semiconductor talent are core inputs. SI003, SI005, SI007, SI012
CI047 Deloitte estimates the AI chip market will be about $500 billion in 2026. SI012
CI048 Public sources provide no evidence of recognized revenue or booked pilot revenue, making revenue quality impossible to underwrite from public data alone. SI001, SI006, SI010
CI049 Public sources provide no evidence of list-to-net pricing or support attach, making Ricursive's gross-margin path impossible to verify today. SI001, SI006, SI014, SI016
CI050 The best public-only financial verdict is that Ricursive is a well-capitalized R&D platform with promising eventual economics but unverified present-day commercialization. SI003, SI006, SI010, SI022
CI051 PwC projects global semiconductor demand rising from $627 billion in 2024 to $1.03 trillion by 2030, with server and network the fastest-growing end market at 11.6% CAGR. SI013
CE001 Ricursive describes itself as a frontier AI lab building self-improving systems starting with chip design. SE001, SE006
CE002 Ricursive’s homepage says the team is behind AlphaChip, RL-CCD, Insta, and C3PO. SE001
CE003 Anna Goldie and Azalia Mirhoseini previously led AlphaChip-related work at Google before founding Ricursive. SE005, SE008, SE014
CE004 DeepMind says AlphaChip generates superhuman or comparable chip layouts in hours instead of weeks or months and has been used across production TPU generations and external chip programs. SE005, SE014
CE005 Ricursive publicly frames its product vision as designless custom silicon where customers specify workloads instead of building full chip-design teams. SE005, SE013, SE022
CE006 Ricursive’s launch and Series A materials say the platform is meant to accelerate and optimize every stage of semiconductor design through a recursive loop between AI and chips. SE006, SE007
CE007 EE Times reports that Ricursive’s first rollout targets workload-specific chip design for third parties. SE013
CE008 TechCrunch reports that Ricursive is building AI tools that design chips rather than selling chips of its own. SE009, SE013
CE009 TechCrunch reports that Nvidia, AMD, Intel, and other chip makers are target customers for Ricursive’s tooling. SE009
CE010 EE Times says Ricursive positions itself as not being an EDA company and says it will not use standard EDA toolchains. SE013
CE011 EE Times says Ricursive’s phase-two goal is an end-to-end model that ingests workloads and outputs GDSII ready for manufacturing. SE013
CE012 StartupHub describes Ricursive’s public roadmap as three stages: accelerate chip design, enable end-to-end co-design, and pursue recursive autonomy. SE022
CE013 StartupHub reports that Ricursive says it is optimizing the detailed flow from architecture design through physical signoff in Phase I. SE022
CE014 StartupHub reports that Ricursive describes an inner loop of AI chip-design tools and an outer self-improving loop that learns from solved problems. SE022
CE015 StartupHub reports that Ricursive presented a static timing-analysis engine with claimed 0.999-plus correlation to leading commercial tools at more than 1000x speed. SE022
CE016 The official Ricursive web surface reviewed in this run was dominated by a homepage and careers pages rather than public docs, API references, or a trust center. SE001, SE002
CE017 Ricursive’s Ashby board listed seven open roles on 2026-07-03 spanning EDA, RTL verification, LLM infrastructure, software infrastructure, research, and security. SE003
CE018 Ricursive’s hiring mix implies a multidisciplinary platform that needs chip-design, model-training, infrastructure, and security functions rather than only research scientists. SE003
CE019 CIOL says Ricursive had no commercial chip in market at the time of coverage and that investors were backing a thesis more than a shipped product. SE012
CE020 CIOL says the gap between research success and commercial reliability remains wide because chip design is deeply risk-averse and requires extensive validation before fabrication. SE012
CE021 DeepMind says AlphaChip uses an edge-based graph neural network and sequential placement process to optimize chip floorplanning under multiple interacting constraints. SE014, SE015
CE022 Google Research’s circuit_training repository exposes a pre-trained checkpoint and scalable training infrastructure, showing that the AlphaChip lineage already has public developer tooling and reusable assets. SE014, SE015
CE023 Synopsys DSO.ai is marketed as reinforcement-learning-driven RTL-to-GDSII optimization inside an existing design flow rather than as workload-to-chip generation. SE016
CE024 Cadence Cerebrus is marketed as AI-driven flow optimization for block and SoC implementation rather than a replacement for the full customer chip-creation stack. SE017
CE025 Cadence ChipStack is marketed as an agentic front-end design and verification workflow rather than a manufacturing handoff engine. SE018
CE026 Siemens Solido is marketed around simulation, variation-aware design, and IP validation inside custom-IC workflows rather than around designless chip delivery. SE019
CE027 Embedded.com says the major EDA vendors are moving toward AI-orchestrated but human-supervised workflows in which engineers remain high-level strategists. SE020
CE028 HCLTech says trusted toolchains and developer tooling must be engineered into chip-design workflows instead of bolted on mid-design. SE021
CE029 No public Ricursive source reviewed in this run disclosed certifications, a trust center, a privacy/security packet, or a formal compliance program. SE001, SE002, SE003
CE030 The Ashby board includes a Founding Security Engineer role, suggesting the security program is being built out but is not yet publicly codified through mature artifacts. SE003
CE031 No public self-serve pricing, API docs, or status page were visible on the official surfaces reviewed, implying a high-touch deployment and support model today. SE001, SE002, SE003
CE032 Lightspeed says advanced chip programs can take two to three years and hundreds of millions of dollars, and frames Ricursive’s opportunity as compressing that timeline to weeks. SE004
CE033 Sequoia says AlphaChip reduced chip floorplanning from months to hours and produced layouts humans would not normally attempt. SE005, SE014
CE034 Ricursive’s Series A release says the founders’ AlphaChip work had been deployed by external semiconductor companies before Ricursive was founded. SE007, SE014
CE035 StartupHub says Ricursive envisions customers sharing requirements and receiving optimized ready-to-build chips across use cases such as AI models, drones, autonomous vehicles, defense, and wearables. SE022
CE036 EE Times says Ricursive wants to democratize custom hardware for organizations with at-scale workloads, including areas such as scientific discovery and healthcare. SE013
CE037 Ricursive’s public moat is much better evidenced in founder pedigree and technical ambition than in disclosed IP estate, customer lock-in, or supply access. SE012, SE013, SE016
CE038 Ricursive’s strongest public reliability evidence comes from the AlphaChip lineage, while public proof of Ricursive-specific deployment, support, and trust controls remains limited. SE012, SE014, SE001
CE039 The broader public lineage Ricursive cites is not just branding; DBLP records RL-CCD as a DAC 2023 paper on concurrent clock and data optimization using attention-based self-supervised reinforcement learning. SE026
CE040 NVIDIA’s EDA lab says INSTA won the DAC'25 Best Paper Award, and the open-source INSTA README describes a differentiable GPU static timing engine with 0.999 correlation to a commercial signoff tool and 25x faster incremental timing analysis. SE027, SE028
CE041 NVIDIA’s EDA lab frames current AI-for-EDA research as spanning RTL design, verification, physical design, signoff, and design-for-manufacturing, illustrating that the technical frontier is expanding beyond single-stage floorplanning. SE027
CE042 NVIDIA’s 2026 C3PO publication page describes commercial-quality global placement via concurrent timing, routability, and wirelength optimization, showing that leading labs are pushing toward integrated physical-design objectives rather than isolated placement heuristics. SE029
CE043 An IndexBox summary of the EE Times interview says Goldie stated Ricursive will not license or use Google intellectual property and argued that independence should make other chip makers more willing to share their data. SE030
CU001 The core Ricursive surfaces reviewed for this chapter do not name a Ricursive production customer or disclose a deployed account. SU001, SU002, SU003, SU004, SU005
CU002 Ricursive publicly positions itself as AI software for semiconductor design rather than as a chip vendor, which implies enterprise design organizations are the intended customers. SU001, SU002, SU004, SU005
CU003 Ricursive’s visible hiring footprint is still engineering-heavy and does not show a scaled public sales or customer-success org. SU009
CU004 Lightspeed says leading-edge silicon programs usually require large teams, two to three years, and hundreds of millions of dollars, which narrows the likely buyer pool to organizations with substantial chip-design budgets. SU006, SU008
CU005 AWS’s Synopsys DSO.ai case study frames AI-assisted chip design as a workflow for complex SoCs, PPA tuning, design reuse, and node migration rather than a consumer-facing product. SU018, SU016
CU006 Cadence markets Cerebrus directly to block engineers and design teams, indicating that physical-design practitioners are the likely day-to-day users of Ricursive-like tools. SU017
CU007 TSMC says it served 534 customers and manufactured 12,682 products in 2025, confirming that advanced silicon development already sits inside a large B2B ecosystem of foundry customers. SU022
CU008 Google Cloud says TPUs are available to external users, so adjacent demand for custom-silicon workflows is not confined to first-party internal Google teams. SU020, SU013
CU009 Microsoft’s Maia 200 launch is another example of workload-specific custom silicon aimed at customer-facing AI inference economics. SU021, SU024
CU010 The likely Ricursive buyer is a compute or silicon program owner, the user is a design or verification team, and the payer is the enterprise funding the silicon roadmap. SU006, SU017, SU018, SU022
CU011 The most plausible Ricursive customer archetypes are frontier AI labs, hyperscalers, large fabless semiconductor companies, and system companies with in-house custom silicon programs. SU006, SU013, SU022, SU024
CU012 DeepMind says AlphaChip has been used across multiple Google TPU generations and was extended by MediaTek, which is the strongest public adjacent proof that the founders have solved a real chip-design workflow for sophisticated users. SU013, SU014
CU013 Sequoia’s podcast says the founders treated the TPU team as their internal customer at Google, showing that their product framing came from a live user workflow rather than pure lab research. SU007
CU014 DeepMind says TPUs are available to external users through Google Cloud, which broadens the practical user surface of the founders’ adjacent AlphaChip work. SU013, SU020
CU015 Ricursive’s launch materials say the company wants to bring its platform to early enterprise, which proves commercialization intent but does not identify any signed account. SU002, SU010
CU016 TechCrunch reported that Ricursive would not name its early customers. SU004
CU017 The same TechCrunch interview said the startup had heard from every big chip-making name and could choose among first development partners, which signals inbound interest but not verified deployment proof. SU004
CU018 Anthropic says it uses over one million Trainium2 chips and that more than 100,000 customers already run Claude on Bedrock, proving that frontier-model labs and their buyers will commit to alternative accelerator platforms at huge scale when economics are strong. SU026, SU027, SU028
CU019 AWS Trainium’s customer page lists Anthropic, Poolside, Decart, Karakuri, AGI House, Hugging Face, Red Hat, and PyTorch, showing adjacent demand from labs, developer ecosystems, and enterprise-software distributors. SU027
CU020 Adjacent custom-silicon customer testimonials emphasize cost, infrastructure availability, throughput, and framework compatibility rather than abstract model novelty. SU027, SU019
CU021 One independent custom-silicon analysis argues that the economics only work once annual inference spend is roughly $500 million or more and workloads are highly uniform. SU024
CU022 The same analysis says hyperscalers were pushed toward custom silicon by cost pressure and by strategic dependence on NVIDIA allocation, roadmap, and pricing. SU024, SU025
CU023 Omdia says foundry expansion, advanced packaging, and HBM supply are structural bottlenecks through at least mid-2027, so design automation alone does not remove deployment friction for end customers. SU025, SU022
CU024 Omdia says foundry customers should lock in 2027 capacity early and secure memory relationships directly, underscoring that downstream customer success depends on supplier orchestration beyond software. SU025
CU025 TSMC says it provides account management, engineering services, online transactions, and an open innovation platform, indicating that chip customers buy into an ecosystem rather than a standalone optimization model. SU022
CU026 Morrison Foerster says export-control enforcement risk extends beyond manufacturers and exporters to the broader AI-chip ecosystem, so customer diligence should include geography and end-use exposure. SU030
CU027 New Scientist recorded expert skepticism about broad “better than humans” AlphaChip claims, which is a reminder not to over-extrapolate founder lineage into current Ricursive commercial proof. SU029, SU013
CU028 Ricursive has not publicly disclosed customer count, deployment count, ARR, NRR, GRR, or renewal data in the sources reviewed for this chapter. SU001, SU002, SU003, SU004
CU029 Because no public contract terms or renewal statistics are disclosed, durability remains unproven rather than negative. SU001, SU003, SU004, SU005
CU030 The public record does not support named logos, NPS, or production-retention claims for Ricursive itself. SU001, SU002, SU003, SU004, SU005
CU031 If Ricursive converts only a small number of reference accounts at first, each one will matter disproportionately because the company has not yet disclosed a diversified installed base. SU001, SU004, SU028
CU032 Ricursive’s commercial motion is likely to be high-touch and partner-heavy because chip-design adoption requires integration with EDA flows, cloud or HPC compute, and foundry processes. SU016, SU017, SU018, SU022
CU033 AWS’s DSO.ai case study says advanced chip-design optimization can require 15 to 30 machines for weeks, so customers will evaluate infrastructure burden along with design quality. SU018
CU034 Cadence customer stories from Broadcom, Imagination, MediaTek, and Renesas show that chip-design-tool buyers expect explicit PPA or productivity proof points before broad adoption. SU017
CU035 Synopsys says DSO.ai optimizes trillions of design recipes across logical and physical domains, so Ricursive is entering a buyer category already saturated with automation claims. SU016, SU018
CU036 Data Center Frontier says Anthropic uses a multi-cloud, multi-accelerator stack across AWS Trainium and Google TPU to preserve supply, pricing, and roadmap resilience. SU028, SU026
CU037 Sophisticated AI buyers appear to prefer optionality rather than single-vendor lock-in, so Ricursive customers may ask for portability across foundry, cloud, and EDA environments. SU028, SU022, SU018
CU038 The strongest supportable public customer proof for Ricursive today is founder lineage plus clear adjacent market demand, not disclosed Ricursive deployment evidence. SU013, SU018, SU026, SU001
CU039 If Ricursive’s first buyers are frontier labs or large silicon teams, the buyer, user, and payer can differ inside one account, which lengthens procurement and validation cycles. SU017, SU018, SU022, SU028
CU040 Anthropic says Claude will be available directly inside AWS with the same account, controls, and billing, which shows that enterprise buyers value procurement rails that fit existing governance. SU026
CU041 AWS Trainium customer references highlight feedback loops with the chip provider and framework teams, suggesting that early Ricursive accounts are likely to demand co-development rather than black-box software sales. SU027
CU042 Trainium customer quotes emphasize lower training cost, higher throughput, and easier access, which are concrete evaluation dimensions a Ricursive reference case would also need to demonstrate. SU027
CU043 Sequoia’s podcast says customers are willing to share data but the founders want it kept private and siloed, implying enterprise confidentiality and data-handling controls will matter in customer diligence. SU007
CR001 Ricursive publicly describes itself as a frontier AI lab building self-improving systems starting with chip design and closing the loop between AI and the hardware that powers it. SR001, SR006
CR002 Ricursive and its backers tie the company’s credibility to AlphaChip-related work that they say has been used across four generations of TPU and by external semiconductor companies. SR001, SR006, SR009
CR003 Lightspeed characterizes high-end chip design as a two-to-three-year process that can consume hundreds of millions of dollars, framing Ricursive’s promised cycle compression against a very expensive baseline. SR003
CR004 TechCrunch reports that Ricursive is building AI tools that design chips rather than selling its own chips, which keeps commercial success tied to external customer adoption of design software and workflows. SR005
CR005 Ricursive told TechCrunch that major chip makers such as Nvidia, AMD, Intel, and other semiconductor companies are the intended customer set, implying a buyer base with deep internal technical capability and bargaining power. SR005
CR006 Ricursive’s January 2026 financing announcement says new capital will be used to scale both research headcount and compute infrastructure, signaling that the model is not a lightweight software go-to-market motion. SR006
CR007 Ricursive’s careers page says the company is hiring across AI, engineering, technical, and operational disciplines, indicating that foundational operating roles are still being built out publicly. SR002
CR008 Public 2026 reporting consistently places Ricursive at roughly $335 million raised, including a $300 million Series A at a $4 billion valuation just months after launch. SR004, SR006, SR007
CR009 CIOL argues that investors are effectively buying a thesis about AI-designed chips before Ricursive has shown a commercial chip or a public production product of its own. SR008
CR010 The strongest adverse public reading is that Ricursive’s case still rests more on founder credibility and prior AlphaChip work than on publicly available product benchmarks or customer deployments. SR005, SR008
CR011 MarketsandMarkets describes the AI EDA market as highly consolidated, with the top five players collectively holding about 70–85% share in 2026. SR012
CR012 Research and Markets says EDA enterprise bundles for comprehensive 3 nm signoff now exceed $1 million per seat and that oligopolistic supply leaves pricing leverage with incumbent vendors. SR013
CR013 Synopsys markets DSO.ai as an autonomous RTL-to-GDSII optimization engine that uses reinforcement learning to search trillions of design recipes across logical and physical domains. SR014
CR014 Cadence says Cerebrus AI Studio can accelerate SoC delivery five-to-ten times while optimizing multi-block, multi-user designs, showing that incumbent toolchains already pitch broad AI productivity gains. SR016
CR015 Cadence’s 2026 ChipStack announcement claims up to 10x productivity gains for front-end design and verification and says early deployments include companies such as Altera, NVIDIA, Qualcomm, and Tenstorrent. SR017
CR016 Siemens says its Solido platform’s AI-enabled variation-aware design, simulation, and IP validation tools are already used by thousands of designers at top semiconductor companies. SR019
CR017 Embedded.com characterizes Cadence, Siemens, and Synopsys as the three dominant EDA players and says their agentic roadmaps still center on AI-orchestrated but human-supervised workflows. SR024
CR018 Synopsys’ investor page frames the company as a trusted silicon-to-systems partner with more than $7 billion in annual revenue and more than 28,000 employees. SR015
CR019 Cadence’s investor page presents the company as a market leader in AI-enabled design for many of the world’s leading semiconductor and systems companies. SR018
CR020 Siemens’ 2026 reliability guidance says stacked 3D IC designs create tightly coupled thermal, mechanical, and electrical interactions such that a single hotspot or power-integrity failure can propagate across dies. SR020
CR021 Siemens’ January 2026 3D IC article says AI models depend on large, heterogeneous, high-quality design datasets and warns that poor curation can amplify bias or produce results engineers cannot trust. SR021
CR022 Industry participants quoted by Semiconductor Engineering say full autonomy is not ready because humans still need to verify that automated systems do what they are intended to do and do not produce non-working chips. SR022
CR023 The same Semiconductor Engineering panel says AI is likelier to automate workflow setup, debug, and verification tasks before it replaces the underlying EDA tools themselves. SR022
CR024 Sony AI’s semiconductor-design interview argues that commercial AI EDA adoption depends on verifiable artifacts, interpretability, and mandatory human signoff for release-critical decisions. SR023
CR025 HCLTech’s 2026 design analysis says secure IP handling, controlled access, encrypted libraries, vendor audits, and version traceability must be engineered into chip-design workflows from the start. SR025
CR026 HCLTech also describes design-to-fab handoff as a point of no return because tape-out errors directly create schedule, wafer, and opportunity-cost losses. SR025
CR027 BIS states that a license is required for advanced-computing items going to D:5 or Macau-headquartered entities and that the authorized IC designer timeline was extended through December 31, 2026. SR026, SR027
CR028 BIS’s May 31, 2026 guidance says the D:5 or Macau license requirement still applies even when the relevant entity is located outside those destinations if its ultimate parent is headquartered there. SR027, SR028
CR029 Holland & Knight says exporters should not treat BIS non-enforcement of the AI Diffusion Rule as a blanket safe harbor and must diligence ultimate-parent headquarters before shipping advanced-computing items. SR028
CR030 Visual Compliance says January 2026 semiconductor export licensing has become evidence-driven and transaction-specific, with heightened remote-access, third-party-testing, and post-license monitoring obligations. SR029
CR031 Deloitte estimates the AI chip market could reach roughly $500 billion in 2026 and says governments are actively funding local fabrication, advanced packaging, and semiconductor R&D for sovereignty reasons. SR010
CR032 PwC’s 2026 semiconductor outlook says geopolitical shifts, export controls, and technology-sovereignty efforts are reshaping supply chains even as AI demand accelerates. SR011
CR033 PwC says major technology companies and cloud providers are already developing their own ASICs to reduce operating costs, which increases buyer sophistication and in-house alternatives for Ricursive’s target accounts. SR011
CR034 Lightspeed frames Ricursive’s upside as compressing silicon design timelines from years to weeks and broadening access to custom silicon beyond companies with massive design teams. SR003
CR035 Public materials say Ricursive aims to extend AI beyond floorplanning into a broader design-and-verification platform and even toward a “designless” model for custom silicon creation. SR005, SR030
CR036 Ricursive’s official site says the team draws from Google DeepMind, Anthropic, NVIDIA, Cadence, Apple, xAI, and top academic institutions, which is a real mitigation against pure execution-naivete. SR001
CR037 Both investor and adverse coverage imply that financing velocity was driven mainly by founder pedigree, technical lineage, and market timing rather than public commercial traction. SR003, SR008
CR038 Ricursive’s own materials describe a small, elite team and broad hiring need, which suggests organizational breadth is still catching up to research ambition. SR001, SR002
CR039 The seed-to-Series-A jump from about $750 million to $4 billion within weeks materially raises the threshold for subsequent proof of customer conversion and durable differentiation. SR004, SR007, SR008
CR040 Visual Compliance highlights that remote end users and IaaS environments now have to be disclosed and controlled in semiconductor export workflows, which is relevant if Ricursive ever supports cross-border cloud evaluation or hosted design environments. SR029
CR041 Embedded.com says exploding SoC complexity and a systemic shortage of specialized engineering talent are core reasons the EDA industry is pushing agentic AI now. SR024
CR042 Siemens warns that a growing share of 3D IC issues is discovered too late during package integration or system bring-up, when fixes are costly or no longer possible. SR020
CR043 HCLTech argues that end-to-end design ownership can cut cycle time by parallelizing workstreams, which implies Ricursive must prove it can own or coordinate more of the stack than a narrow point solution can. SR025
CR044 TechCrunch says Ricursive will not name early customers publicly even though the founders say they have heard from every big chipmaking name and can choose development partners. SR005
CR045 Across the reviewed public corpus, Ricursive’s narrative is much richer on funding, pedigree, and vision than on revenue, named production customers, or benchmarked product economics. SR001, SR003, SR006, SR008
CR046 Research and Markets says final SoC handoff still depends on certified timing and electrical-rule reports accepted by foundries, which reinforces the moat of established back-end flows and qualified toolchains. SR013
CR047 The highest-leverage diligence package is a combination of named design-partner evidence, benchmarked verification results against incumbent flows, export-control workflow documentation, and a compute-burn runway bridge. SR005, SR008, SR025, SR028, SR029
CV001 Ricursive's January 2026 financing set a high reference price for this chapter's analysis, implying about $13.3 of post-money equity value for every $1 of new primary capital raised. SV001, SV002, SV004, SV005
CV002 Ricursive had previously raised a $35 million seed round at about a $750 million valuation in December 2025. SV003, SV004
CV003 TechCrunch reported that Ricursive had raised $335 million total by February 2026. SV002, SV003
CV004 The January 2026 Series A syndicate included Lightspeed, DST Global, NVentures, Felicis, 49 Palms, Radical Ventures, and Sequoia Capital. SV001, SV004, SV005
CV005 Ricursive was founded by Anna Goldie and Azalia Mirhoseini, whose work on AlphaChip underpins the company’s credibility in AI-driven chip design. SV001, SV003, SV011, SV013
CV006 Ricursive says its platform aims to accelerate semiconductor design and eventually let AI design the silicon substrate for future AI systems. SV001, SV002, SV011
CV007 TechCrunch said AlphaChip could generate high-quality chip layouts in about six hours versus a process that often takes human designers a year or more. SV003
CV008 Ricursive coverage describes AlphaChip-derived methods as learning across designs and extending from placement toward broader design verification tasks. SV003, SV006
CV009 New Scientist reported that independent experts disputed whether AlphaChip had publicly proven superiority over expert human designers or commercial tools. SV019
CV010 New Scientist also quoted a critic who said reinforcement-learning approaches can require orders of magnitude more compute than methods used in commercial chip-design tools. SV019
CV011 Synopsys markets DSO.ai as autonomous RTL-to-GDSII optimization that searches trillions of design recipes to improve performance, power, and area. SV014, SV016
CV012 Cadence markets Cerebrus as an AI-driven chip-design optimizer that can automate multi-block flow exploration and improve PPA and productivity. SV015, SV017
CV013 Forbes reported in February 2026 that Cadence had broadened its AI automation stack with what it called the first AI super-agent for chip design. SV017
CV014 Ricursive therefore enters a market where incumbent EDA vendors already ship AI-assisted automation with customer references and distribution. SV014, SV015, SV016, SV017
CV015 Google TPU, AWS Trainium, and Microsoft Maia sources show hyperscalers continue investing aggressively in custom AI silicon. SV020, SV021, SV022
CV016 BIS, CSIS, and Morrison Foerster sources show export-control and compliance scrutiny remained active across advanced AI and semiconductor ecosystems in 2025-2026. SV031, SV032, SV033, SV034
CV017 That policy backdrop can narrow customer sets or slow commercialization for AI-chip design platforms that operate across sensitive semiconductor programs. SV031, SV033, SV034
CV018 As of July 2026, Synopsys showed about $83.70 billion of market capitalization and about $8.00 billion of TTM revenue. SV023, SV024, SV039
CV019 As of July 2026, Cadence showed about $102.91 billion of market capitalization and about $5.52 billion of TTM revenue. SV025, SV026, SV037
CV020 As of July 2026, NVIDIA showed about $4.718 trillion of market capitalization and about $215.93 billion of TTM revenue. SV027, SV028, SV035, SV038
CV021 As of July 2026, AMD showed about $844.35 billion of market capitalization and about $34.63 billion of TTM revenue. SV029, SV030, SV036
CV022 Those four public references imply simple market-cap-to-revenue proxies of about 10.5x for Synopsys, 18.6x for Cadence, 21.9x for NVIDIA, and 24.4x for AMD. SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV023 Across the four-company set, the simple average market-cap-to-revenue proxy is about 18.8x and the median is about 20.2x. SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV024 None of the cited Ricursive sources publicly disclose current revenue, ARR, gross margin, or customer count. SV001, SV002, SV003, SV011
CV025 The current $4 billion mark is therefore being underwritten mainly on team quality, technical promise, and market narrative rather than on public operating metrics. SV001, SV002, SV003, SV007, SV011
CV026 The jump from a $750 million seed valuation to a $4 billion Series A post-money valuation is about 5.33x. SV003, SV004
CV027 A $300 million primary round at a $4 billion post-money valuation implies a roughly $3.7 billion pre-money valuation and about 7.5% new-money dilution before fees. SV001
CV028 Total disclosed capital raised of $335 million equals about 8.4% of the $4 billion post-money valuation. SV003, SV004
CV029 Lightspeed said Ricursive had already achieved technical progress, but the public materials do not quantify that progress or identify paying customers. SV001, SV007
CV030 Ricursive’s own website emphasizes mission, hiring, and long-horizon compute ambitions rather than current customer deployments. SV011, SV012
CV031 The Ashby jobs page shows Ricursive actively hiring across research and engineering roles, consistent with a buildout phase rather than a mature revenue-scaling phase. SV012
CV032 Expanding the team and compute infrastructure implies meaningful cash burn before monetization is publicly proven. SV001, SV012
CV033 Export-control complexity adds go-to-market friction even if Ricursive sells design tooling rather than finished chips, because customer programs still sit inside controlled semiconductor ecosystems. SV031, SV033, SV034
CV034 The January 2026 Series A can still be rational if Ricursive becomes a strategically important enabling layer for hyperscalers or chip vendors. SV007, SV015, SV020, SV021, SV022
CV035 TechCrunch reported that every big chip-making name had contacted the founders and that Nvidia invested, which supports strategic interest but not booked revenue. SV003
CV036 New Scientist’s technical criticism plus incumbent EDA competition create a credible adverse case that Ricursive’s valuation may be outrunning reproducible commercial advantage. SV014, SV015, SV017, SV019
CV037 A bear case emerges if Ricursive cannot demonstrate customer-relevant speed or PPA gains versus incumbent workflows or cannot convert early partners into repeat paid programs. SV014, SV015, SV019
CV038 A base case assumes Ricursive converts investor enthusiasm into early paid programs but still needs time to prove durable economics, supporting a valuation corridor roughly around the current mark. SV001, SV007, SV015
CV039 A bull case requires measurable design-cycle compression plus compute-efficiency gains on important chip programs, allowing Ricursive to sustain scarcity value above the current mark. SV001, SV007, SV015, SV020, SV021, SV022
CV040 Because the January 2026 round already prices in substantial future success, entry discipline should be milestone-based rather than prestige-based. SV001, SV003, SV019
CV041 Crunchbase reported that more than 40% of 2026 seed and Series A investment had gone to rounds of $100 million or more, confirming that giant early-stage financings were a real market backdrop rather than a Ricursive-only anomaly. SV049
CV042 Direct 2025-2026 peer financings span Unconventional AI at a $4.5 billion seed valuation, Rebellions at roughly a $2.34 billion pre-IPO valuation, Inferact at an $800 million seed valuation, and XCENA at a $570 million valuation, showing that private markets will pay aggressively for scarce AI-infrastructure narratives. SV043, SV044, SV045, SV046
CV043 If Ricursive eventually traded on a Synopsys-like 10.5x revenue multiple, a $6 billion bull outcome would still require about $570 million of annual revenue. SV023, SV024
CV044 At a $3 billion bear valuation, Ricursive would still need about $160 million of revenue on the 18.8x four-comp average or about $287 million on the Synopsys proxy to justify the mark. SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV045 The most defensible current stance is track / research-more with medium confidence, high risk, and a stretched valuation view. SV001, SV003, SV019, SV023, SV024, SV025, SV026
CV046 Another private round or strategic partnership is easier to support from current evidence than a near-term IPO-style valuation framework. SV018, SV020, SV023, SV024, SV025, SV026
CV047 The gating diligence asks are revenue model, named paying customers, benchmarked performance versus incumbents, gross-margin structure, and the rights embedded in the $300 million Series A. SV001, SV014, SV015
CV048 Public comparables such as NVIDIA, AMD, Cadence, and Synopsys maintain ongoing filing or annual-report disclosure surfaces, highlighting how far Ricursive remains from IPO-grade transparency. SV035, SV036, SV038, SV040, SV041, SV042
CV049 At the current $4 billion headline mark, the scenario set implies roughly 0.6x-0.8x gross MOIC in the bear case, about 0.9x-1.2x in the base case, and about 1.5x-2.0x in the bull case before any dilution, employee refresh, or liquidation-preference effects. SV001, SV023, SV024, SV025, SV026, SV027, SV028, SV029, SV030
CV050 Public financing coverage discloses headline valuation, investors, and use of proceeds but not liquidation preferences, participation terms, ratchets, or board-control rights, so preference overhang cannot be underwritten from public evidence alone. SV001, SV002, SV003, SV004
CV051 MatX and Cognichip show capital is still flowing into adjacent AI-chip and chip-design tooling bets, but their financings emphasize technical promise and time-to-market compression rather than disclosed durable revenue, limiting their usefulness as price-support comparables for Ricursive. SV047, SV048
来源
编号出版方标题引文
SO001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
SO002 Ricursive Intelligence Careers - Riculsive Intelligence
SO003 Ashby Ricursive Intelligence Jobs
SO004 Ashby General Application @ Ricursive Intelligence
SO005 Ashby LLM Modeling and Scaling Researcher @ Ricursive Intelligence
SO006 Ashby RTL and Design Verification Engineer @ Ricursive Intelligence
SO007 Ashby Member of Technical Staff - SWE Infrastructure @ Ricursive Intelligence
SO008 Ashby EDA Algorithm Engineer @ Ricursive Intelligence
SO009 Ashby LLM Infra Engineer @ Ricursive Intelligence
SO010 Ashby Founding Security Engineer @ Ricursive Intelligence
SO011 Lightspeed Venture Partners Ricursive Intelligence
SO012 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SO013 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SO014 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch
SO015 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months
SO016 Ricursive Intelligence / PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SO017 Ricursive Intelligence / PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SO018 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SO019 Tech Funding News From Google’s AlphaChip to $4B: Ricursive becomes an AI chip-design unicorn
SO020 CIOL Ricursive’s $4B Valuation Tests Investor Faith in AI-Designed Chips
SO021 Google DeepMind How AlphaChip transformed computer chip design
SO022 UBOS Ricursive Intelligence Secures $335M Funding at $4B Valuation – AI Startup Revolutionizes Chip Design
SO023 Business 2.0 News Ricursive Intelligence Raises $300M Series A at $4B Valuation for AI Chip Design
SO024 Silicon Valley Daily Ricursive Intelligence Scores $400 Million Series A
SO025 Seedtable Ricursive Intelligence — Funding, Investors & Team
SM001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
SM002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SM003 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months
SM004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch
SM005 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SM006 Sequoia Capital How Ricursive Intelligence's Founders are Using AI to Shape The Future of Chip Design
SM007 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SM008 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market
SM009 Cadence Design Systems Cadence Cerebrus Intelligent Chip Explorer
SM010 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design
SM011 Nature A graph placement methodology for fast chip design
SM012 New Scientist Google says its AI designs chips better than humans – experts disagree
SM013 Amazon Web Services AWS Trainium
SM014 Google Cloud Tensor Processing Units (TPUs)
SM015 Microsoft Maia 200: The AI accelerator built for inference - The Official Microsoft Blog
SM016 SEMI Global Fab Equipment Investment Expected to Reach $110 Billion in 2025
SM017 Bureau of Industry and Security Commerce Strengthens Export Controls to Restrict China’s Capability to Produce Advanced Semiconductors for Military Applications
SM018 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem
SM019 CompaniesMarketCap Synopsys (SNPS) - Revenue
SM020 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue
SM021 CompaniesMarketCap Synopsys (SNPS) - Market capitalization
SM022 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization
SM023 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SM024 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI
SM025 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SP001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
SP002 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SP003 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SP004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch | TechCrunch
SP005 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SP006 Synopsys Generative and Agentic AI Transforming Chip Design | Synopsys
SP007 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market | Amazon Web Services
SP008 Cadence Cadence Cerebrus Intelligent Chip Explorer
SP009 Cadence Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification
SP010 Siemens Solido Solutions
SP011 Embedded.com A Look at Agentic AI in the EDA Engineering Workflow
SP012 Google DeepMind How AlphaChip transformed computer chip design
SP013 New Scientist Client Challenge
SP014 Google Research Google says its AI designs chips better than humans – experts disagree
SP015 Google Cloud GitHub - google-research/circuit_training
SP016 Amazon Web Services Tensor Processing Units (TPUs)
SP017 Microsoft AWS Trainium
SP018 Synopsys Investor Relations Maia 200: The AI accelerator built for inference - The Official Microsoft Blog
SP019 Cadence Investor Relations Investor Relations & Investor Resources
SP020 NVIDIA Investor Relations Cadence Investor Relations | CDNS Financials & Investor News
SP021 AMD Investor Relations NVIDIA Corporation - Home
SP022 TechCrunch Investors
SP023 MatX Qualcomm - Investor Relations
SP024 Rebellions Financial Results
SP025 CNBC Cognichip wants AI to design the chips that power AI, and just raised $60M to try | TechCrunch
SP026 Crunchbase News MatX One and our Series B | MatX
SP027 Data Center Dynamics Rebellions Closes $400 Million Pre-IPO and Launches RebelRack™ and RebelPOD™ to Accelerate Global Expansion - Rebellions
SP028 Crunchbase News Samsung-backed AI chip firm Rebellions raises $400 million ahead of IPO
SP029 PR Newswire Sector Snapshot: Semiconductor Startup Funding Still Running Hot
SP030 TechCrunch Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SP031 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SP032 CompaniesMarketCap Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SP033 CompaniesMarketCap AI chip startup Rebellions raises $400 million at $2.3B valuation in pre-IPO round | TechCrunch
SP034 CompaniesMarketCap Q1 2026 Shatters Venture Funding Records As AI Boom Pushes Startup Investment To $300B
SP035 CompaniesMarketCap Synopsys (SNPS) - Market capitalization
SP036 CompaniesMarketCap Synopsys (SNPS) - Revenue
SP037 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization
SP038 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue
SP039 CompaniesMarketCap NVIDIA (NVDA) - Market capitalization
SI001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SI002 Ricursive Intelligence Careers - Riculsive Intelligence At Ricursive, we search for exceptional talent across a variety of AI, engineering, technical, and operational disciplines.
SI003 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SI004 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SI005 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch
SI006 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months Ricursive is building AI tools that design chips, not the chips themselves.
SI007 PR Newswire / Ricursive Intelligence Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design The new funding will be used to scale Ricursive's world-class research and engineering team and significantly expand its compute infrastructure.
SI008 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SI009 Tech Funding News From Google’s AlphaChip to $4B: Ricursive becomes an AI chip-design unicorn
SI010 CIOL Ricursive’s $4B Valuation Tests Investor Faith in AI-Designed Chips At this stage, Ricursive’s case rests largely on the credibility of its founders and their prior work, not on publicly available benchmarks or products.
SI011 DeepMind How AlphaChip transformed computer chip design The method has been used to design superhuman chip layouts in the last three generations of Google’s custom AI accelerator, the Tensor Processing Units (TPUs).
SI012 Deloitte 2026 Global Semiconductor Industry Outlook Deloitte now estimates that the AI chip market in 2026 will be about US$500B.
SI013 PwC PwC_Semiconductor and Beyond_2026 The global semiconductor market is projected to grow from $627B (2024) to $1,030B (2030F).
SI014 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI Synopsys DSO.ai reduces design time, improves design quality, and helps to unlock the full PPA potential.
SI015 Synopsys Generative and Agentic AI Transforming Chip Design
SI016 Cadence Cadence Cerebrus AI Studio | Digital Design and Signoff This tool accelerates chip delivery time by 5X to 10X while achieving superior performance, power, and area (PPA) targets.
SI017 Cadence Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification
SI018 Siemens EDA Solido Solutions The Solido variation-aware design, IP validation, library characterization and simulation solutions are used by 1000s of designers at the top semiconductor companies worldwide.
SI019 Synopsys Investor Relations & Investor Resources $7+ billion annual revenue; 28,000+ employees.
SI020 StockLight / Cadence Design Systems filing Cadence Design Systems Annual Report 2026 Product and maintenance $4,822 million, 91%; Services $475 million, 9%; Total revenue $5,297 million.
SI021 StockLight / Synopsys filing Synopsys Annual Report 2025 Revenue $7,054.2 million; Cost of revenue $1,623.5 million.
SI022 Semiconductor Engineering AI’s Potential And Limitations In Chip Design It will not replace the tools themselves... the human is going to have to be in control for quite some time.
SI023 Siemens Ensure 3D IC Multiphysics Reliability for AI Systems at Scale A single thermal, a single stress hotspot, or power integrity failure can propagate across dies, compromising system-level reliability.
SI024 Siemens AI is reshaping the 3D IC design ecosystem: Key trends to watch in 2026 Multi-chiplet planning, inter-die connectivity, and system-level modeling all introduce challenges that strain traditional EDA workflows.
SI025 HCLTech Chip design in the AI era Performance-per-watt gains increasingly come from chiplets, advanced packaging and smarter physical design, not just node shrinks.
SE001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence
SE002 Ricursive Intelligence Careers - Riculsive Intelligence
SE003 Ashby Ricursive Intelligence Jobs
SE004 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SE005 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SE006 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SE007 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design
SE008 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch | TechCrunch
SE009 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months | TechCrunch
SE010 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SE011 Tech Funding News From Google’s AlphaChip to $4B: Ricursive becomes an AI chip-design unicorn
SE012 CIOL Ricursive’s $4B Valuation Tests Investor Faith in AI-Designed Chips
SE013 EE Times Startup Ricursive to Create an End-to-End AI Model for Chip Design
SE014 Google DeepMind How AlphaChip transformed computer chip design
SE015 Google Research GitHub - google-research/circuit_training
SE016 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SE017 Cadence Cadence Cerebrus Intelligent Chip Explorer
SE018 Cadence Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification
SE019 Siemens Solido Solutions
SE020 Embedded.com A Look at Agentic AI in the EDA Engineering Workflow
SE021 HCLTech Chip design in the AI era | HCLTech
SE022 StartupHub.ai AI Designs Its Own Chips with Ricursive
SE023 International AI Safety Report International AI Safety Report 2026
SE024 Siemens Ensure 3D IC Multiphysics Reliability for AI Systems at Scale - Semiconductor Packaging
SE025 Siemens AI is reshaping the 3D IC design ecosystem: Key trends to watch in 2026 - Semiconductor Packaging
SE026 DBLP Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning.
SE027 NVIDIA NVIDIA Design Automation Research Group
SE028 NVIDIA INSTA/README.md at main · NVlabs/INSTA
SE029 NVIDIA C3PO: Commercial-Quality Global Placement via Coherent, Concurrent Timing, Routability, and Wirelength Optimization | NVIDIA Electronic Design Automation Research
SE030 IndexBox Ricursive Aims to Transform Chip Design with End-to-End AI Model, Raises $335M - News and Statistics - IndexBox
SU001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Ricursive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SU002 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence Ricursive Intelligence will leverage the funding to scale its AI research, expand its compute infrastructure, and bring its platform to early enterprise.
SU003 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design The new funding will be used to scale Ricursive’s world-class research and engineering team and significantly expand its compute infrastructure.
SU004 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months While the young startup won’t name its early customers, the founders say that they’ve heard from every big chip making name you can imagine.
SU005 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch Ricursive is building AI tools that design chips, not the chips themselves.
SU006 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SU007 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design While customers are willing to share data, Anna and Azalia want to keep it private and siloed.
SU008 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI Every frontier model, every hyperscaler, and every new AI-native product ultimately runs into the same constraint: how quickly—and how affordably—we can design the chips underneath it all.
SU009 Ashby Ricursive Intelligence Jobs Open Positions (7)
SU010 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design
SU011 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI
SU012 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SU013 Google DeepMind How AlphaChip transformed computer chip design External organizations are also adopting and building on AlphaChip. For example, MediaTek... extended AlphaChip to accelerate development of their most advanced chips while improving power, performance and chip area.
SU014 Nature A graph placement methodology for fast chip design
SU015 GitHub google-research/circuit_training
SU016 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SU017 Cadence Cadence Cerebrus Intelligent Chip Explorer We use a wide portfolio of Cadence solutions across our business units, and we have seen outstanding PPA improvements from the use of the AI capabilities of Cadence Cerebrus.
SU018 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market This type of AI computation could take 15-30 machines running for weeks at a time... to achieve the PPA targets of a complex chip design.
SU019 Amazon Web Services AWS Trainium
SU020 Google Cloud Tensor Processing Units (TPUs)
SU021 Microsoft Maia 200: The AI accelerator built for inference
SU022 TSMC Dedicated IC Foundry In 2025, TSMC served 534 customers and manufactured 12,682 products.
SU023 Hashrate Index Hyperscaler AI ASIC Market: Google, AWS, Microsoft & More
SU024 Industry Talks Tech The Custom Silicon Arms Race: Why Every Hyperscaler Is Building Its Own Chip The economics only work above ~$500M in annual inference spend with highly uniform workloads and a 5+ year engineering commitment.
SU025 Omdia The $100 Billion Wait: Why Hyperscale Ambitions are Hitting the Foundry Wall Most of the massive capacity intended to save the supply chain won't hit high-volume manufacturing until mid-2027.
SU026 Anthropic Anthropic and Amazon expand collaboration for up to 5 gigawatts of new compute We have worked closely with Amazon since 2023 and over 100,000 customers now run Claude on Amazon Bedrock.
SU027 Amazon Web Services AI Accelerator - AWS Trainium Customers With almost a million Trainium2 chips training and serving Claude today, we’re excited about Trainium3.
SU028 Data Center Frontier Inside Anthropic’s Multi-Cloud AI Factory: How AWS Trainium and Google TPUs Shape Its Next Phase Anthropic is effectively reserving a substantial share of Google’s future TPU capacity and tying that scale directly into Google Cloud’s enterprise AI go-to-market.
SU029 New Scientist Google says its AI designs chips better than humans – experts disagree Google says its AI designs chips better than humans – experts disagree.
SU030 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem Recent actions by the U.S. Department of Commerce’s Bureau of Industry and Security (BIS) and the U.S. Department of Justice (DOJ) highlight how enforcement risk extends beyond manufacturers and exporters to include the broader AI chip ecosystem.
SR001 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI - Riculsive Intelligence Backed by $335M from Sequoia, Lightspeed, DST, and NVentures, we are scaling a small, elite team to solve the most important bottlenecks in AI and chip design.
SR002 Ricursive Intelligence Careers - Riculsive Intelligence
SR003 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI The most performant silicon takes large teams of engineers upwards of two to three years and hundreds of millions of dollars to design.
SR004 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch | TechCrunch
SR005 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months | TechCrunch Ricursive is building AI tools that design chips, not the chips themselves.
SR006 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design The new funding will be used to scale Ricursive's world-class research and engineering team and significantly expand its compute infrastructure.
SR007 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SR008 CIOL Ricursive’s $4B Valuation Tests Investor Faith in AI-Designed Chips At this stage, Ricursive’s case rests largely on the credibility of its founders and their prior work, not on publicly available benchmarks or products.
SR009 Google DeepMind How AlphaChip transformed computer chip design AlphaChip has generated superhuman chip layouts used in every generation of Google’s TPU since its publication in 2020.
SR010 Deloitte Insights 2026 Global Semiconductor Industry Outlook
SR011 PwC PwC_Semiconductor and Beyond_2026
SR012 MarketsandMarkets Synopsys, Inc. (US) and Cadence Design Systems, Inc. (US) are Leading Players in the AI EDA Market
SR013 Research and Markets Electronic Design Automation Tools (EDA) - Market Share Analysis, Industry Trends & Statistics, Growth Forecasts (2026-2031)
SR014 Synopsys DSO.ai: AI-Driven Design Applications | Synopsys AI
SR015 Synopsys Investor Relations & Investor Resources
SR016 Cadence Cadence Cerebrus AI Studio | Digital Design and Signoff
SR017 Cadence Cadence Unleashes ChipStack AI Super Agent, Pioneering a New Frontier in Chip Design and Verification
SR018 Cadence Cadence Investor Relations | CDNS Financials & Investor News
SR019 Siemens Solido Solutions
SR020 Siemens Ensure 3D IC Multiphysics Reliability for AI Systems at Scale - Semiconductor Packaging
SR021 Siemens AI is reshaping the 3D IC design ecosystem: Key trends to watch in 2026 - Semiconductor Packaging
SR022 Semiconductor Engineering AI’s Potential And Limitations In Chip Design
SR023 Silicon Semiconductor AI and the future of semiconductor design - Silicon Semiconductor News
SR024 Embedded.com A Look at Agentic AI in the EDA Engineering Workflow
SR025 HCLTech Chip design in the AI era | HCLTech
SR026 Bureau of Industry and Security Homepage | Bureau of Industry and Security
SR027 Bureau of Industry and Security Guidance Regarding Enforcement of License Requirements for Advanced Computing Items for Entities Headquartered in Country Group D:5 and Macau [May 31, 2026]
SR028 Holland & Knight BIS Publishes Guidance Regarding License Requirements for Advanced Computing Items | Insights | Holland & Knight
SR029 Visual Compliance BIS Revises Semiconductor Export Licensing Rule for China: Understand the Trade Compliance Impact | Visual Compliance: International Trade Compliance Software
SR030 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SV001 PR Newswire Ricursive Intelligence Raises $300 Million Series A at $4 Billion Valuation to Accelerate AI-Driven Semiconductor Design Ricursive Intelligence ... announced a $300 million Series A funding round led by Lightspeed Venture Partners at a $4 billion post-money valuation.
SV002 TechCrunch AI chip startup Ricursive hits $4B valuation 2 months after launch
SV003 TechCrunch How Ricursive Intelligence raised $335M at a $4B valuation in 4 months
SV004 Crunchbase News AI Lab Ricursive Intelligence Lands $300M Series A At $4B Valuation Less than Two Months After Launch
SV005 Data Center Dynamics Ricursive Intelligence raises $300m against $4bn valuation for AI chip design platform
SV006 SiliconANGLE Ricursive Intelligence nabs $300M to speed up chip design with AI
SV007 Lightspeed Venture Partners Investing in Ricursive Intelligence: AI for Chip Design and Chip Design for AI
SV008 Felicis Felicis's Series A in Ricursive Intelligence: A step-change on the path to AGI
SV009 PR Newswire Ricursive Intelligence Launches Frontier AI Lab to Transform Semiconductor Design and Accelerate Path Toward Artificial Superintelligence
SV010 Converge Digest Ricursive Intelligence Aims to Accelerate Semiconductor Design
SV011 Ricursive Intelligence Recursive Self-Improvement via AI for Chip Design & Chip Design for AI
SV012 Ashby Ricursive Intelligence Jobs
SV013 Sequoia Capital How Ricursive Intelligence’s Founders are Using AI to Shape The Future of Chip Design
SV014 Synopsys DSO.ai: AI-Driven Design Applications
SV015 Cadence Cadence Cerebrus Intelligent Chip Explorer
SV016 Amazon Web Services Boost Chip Design with AI: How Synopsys DSO.ai on AWS Delivers Lower Power and Faster Time-to-Market
SV017 Forbes This Cadence AI Super Agent Is World’s First To Automate Chip Design
SV018 Nature A graph placement methodology for fast chip design
SV019 New Scientist Google says its AI designs chips better than humans – experts disagree Google DeepMind claims its AlphaChip AI method can deliver “superhuman” chip designs ... but independent experts say public proof is lacking.
SV020 Google Cloud Tensor Processing Units (TPUs)
SV021 Amazon Web Services AWS Trainium
SV022 Microsoft Maia 200: The AI accelerator built for inference
SV023 CompaniesMarketCap Synopsys (SNPS) - Market capitalization
SV024 CompaniesMarketCap Synopsys (SNPS) - Revenue
SV025 CompaniesMarketCap Cadence Design Systems (CDNS) - Market capitalization
SV026 CompaniesMarketCap Cadence Design Systems (CDNS) - Revenue
SV027 CompaniesMarketCap NVIDIA (NVDA) - Market capitalization
SV028 CompaniesMarketCap NVIDIA (NVDA) - Revenue
SV029 CompaniesMarketCap AMD (AMD) - Market capitalization
SV030 CompaniesMarketCap AMD (AMD) - Revenue
SV031 Bureau of Industry and Security Commerce strengthens export controls to restrict China’s capability to produce advanced semiconductors used for military applications
SV032 Bureau of Industry and Security AI policy statement on training AI models
SV033 Center for Strategic and International Studies Understanding U.S. Allies’ Current Legal Authority to Implement AI and Semiconductor Export Controls
SV034 Morrison Foerster Managing Export Control Risks in the AI Chip Ecosystem
SV035 NVIDIA Investor Relations NVIDIA Corporation - Financial Info SEC Filings
SV036 AMD Investor Relations AMD SEC Filings
SV037 Cadence Investor Relations Cadence SEC Filings
SV038 NVIDIA Investor Relations Annual Reports and Proxies
SV039 Synopsys Investor Relations Synopsys Investor Overview
SV040 Synopsys Investor Relations Synopsys SEC Filings
SV041 U.S. Securities and Exchange Commission Cadence Design Systems 2025 Form 10-K XBRL Viewer
SV042 U.S. Securities and Exchange Commission AMD 2025 Form 10-K XBRL Viewer
SV043 TechCrunch Unconventional AI confirms its massive $475M seed round
SV044 TechCrunch AI chip startup Rebellions raises $400 million at $2.3B valuation in pre-IPO round
SV045 TechCrunch This chip startup just raised $135M on a bet that AI's biggest bottleneck isn't compute -- it's memory
SV046 TechCrunch Inference startup Inferact lands $150M to commercialize vLLM
SV047 TechCrunch Nvidia challenger AI chip startup MatX raised $500M
SV048 TechCrunch Cognichip wants AI to design the chips that power AI, and just raised $60M to try
SV049 Crunchbase News A Growing Share Of Seed And Series A Funding Is Going To Giant Rounds