Celero Communications

1.1 Identity and operating scope

Celero Communications is a private semiconductor company founded in 2024 and headquartered in Irvine, California, with company-disclosed design centers in Canada and Argentina. It develops coherent digital signal processors intended to deliver high-bandwidth, low-power optical connectivity for AI accelerator clusters and cloud data centers. That identity is important because web results also contain Celero Commerce, an unrelated payment-processing company acquired by Deluxe; evidence about that business must not be attributed to Celero Communications. The assigned evidence establishes the product category and locations, but does not establish current revenue or ARR, named customers, shipment volumes, production design wins, or 2026 headcount. A CapitalG post described a 100-person team in November 2025, which is a dated investor statement rather than a current employee count.[CO001, CO002, CO003, CO006, CO015]

1.2 Leadership and governance

Co-founders Nariman Yousefi and Oscar Agazzi occupy the central executive and technical roles: Yousefi is chief executive and Agazzi is chief technology officer. CapitalG and the company describe both as veterans of Marvell, Inphi, Broadcom, and ClariPhy who worked on prior DSP and networking products. Public financing materials also identify investor representatives James Luo, Stefan Dyckerhoff, and Gavin Baker as board members. This is strong evidence of domain-specific founder-market fit and investor engagement, but it also concentrates much of the externally visible operating credibility in two founders. The available pool does not provide a complete board roster, committee structure, voting rights, succession plan, or broader executive bench, so governance quality and key-person mitigation cannot yet be underwritten.[CO004, CO005, CO011, CO016]

1.3 Capitalization and stakeholders

Celero announced $140 million of total funding in November 2025, comprising a $100 million Series B and $40 million from earlier rounds. In October 2026, Orrick reported a $275 million Series C, $415 million of total capital raised, and a valuation above $3 billion. CapitalG, Atreides Management, and Valor Equity Partners led the Series C, while Sutter Hill Ventures and Maverick Silicon continued as investors. These figures describe financing proceeds and a transaction valuation; they do not establish cash currently available, revenue, ARR, cash burn, runway, or the economics of any secondary sales or debt. Multiples presents a material data-quality conflict: its summary reports $413 million raised, while its own detailed Series C narrative says $415 million. The primary-adjacent Orrick and investor accounts support using $415 million, with the discrepancy retained rather than silently reconciled.[CO007, CO008, CO009, CO010, CO013]

1.4 Milestones and diligence boundary

The disclosed chronology shows unusually fast capitalization and technical progression: founding and seed financing in 2024, a Series A later that year, the Series B in November 2025, and the Series C in 2026. Orrick and CapitalG report that Celero validated 2nm coherent DSP silicon intended to span 1.6T through 3.2T connectivity. That milestone narrows one historical concern raised by Tech in Asia, which in November 2025 highlighted missing process-node and tapeout disclosures. It does not close the remaining diligence gaps around baud rate, measured power, production yield, customer qualification, partnerships, and commercial shipments. The timeline therefore records disclosed events rather than treating financing or silicon validation as proof of market adoption. Investment diligence should require primary operating data, customer references, capitalization documents, and a current organization chart before relying on the valuation or scale narrative.[CO001, CO006, CO007, CO008, CO012, CO014]

1.5 Exhibits

2.1 Market boundary and substitutes

Celero's defensible market boundary is much narrower than "AI data centers." The core category is coherent DSP silicon embedded in optical links used to connect accelerators, racks, buildings, and data centers. Celero and CapitalG describe data-center-specific coherent DSPs spanning AI accelerator clusters and cloud data-center connections; EquityZen similarly identifies data-center networks and AI acceleration clusters. Broader optical transport, complete transceivers, switches, fiber, and total AI infrastructure investment are demand context rather than Celero TAM. Status-quo and adjacent substitutes include copper for short reaches, PAM4 optics at established data rates, legacy telecom coherent for longer links, and emerging LPO, LRO, and CPO architectures that can reduce standalone DSP content. This boundary centers the analysis on DSP content where coherent performance is actually required.[CM001, CM002, CM003, CM004]

2.2 Evidence-constrained sizing

Public evidence supports several non-equivalent sizing lenses, not a clean TAM/SAM/SOM. A Celero-issued release cites nearly $7 trillion of global data-center investment through 2030, including about $5.2 trillion for AI workloads, but those figures include compute, power, construction, and other spend far outside DSPs. Dell'Oro estimates reported by Converge Digest put 2026 optical-transport manufacturer revenue above $18 billion after a 16% forecast increase, while an earlier Dell'Oro forecast reported by RCR Wireless put the market at $19 billion in 2029 on 5% annual growth. LightCounting provides the closest component lens: more than $2 billion of 1.6T chipset sales in 2026 and more than eight million coherent-DSP units by 2031. Different periods, products, and units make these contextual bounds, not additive layers.[CM005, CM006, CM007, CM008, CM009]

2.3 Buyers, users, and budget path

The economic chain separates the immediate silicon buyer from the end payer. Optical module and system vendors are the likely direct DSP integrators; their product, engineering, and sourcing teams must qualify silicon into transceivers or platforms. Hyperscalers, cloud operators, and service providers ultimately fund deployments through network and data-center capital budgets, while network architects and cluster operators are the users most exposed to reach, power, bandwidth density, and reliability. Cisco reports that hyperscalers account for most coherent-pluggable deployments and that about 350 service providers also deploy the optics. Public sources do not establish Celero's contracting model, module partners, budget ownership at named customers, or whether the company sells silicon directly to end operators.[CM010, CM011]

2.4 Growth drivers and adoption constraints

Demand is supported by AI clusters spanning more accelerators and facilities, higher link rates, and greater data-center-interconnect traffic. Dell'Oro data reported by Converge Digest show direct DCI purchases growing an estimated 40% year over year in the first quarter of 2026. Adoption is not frictionless: supplier backlogs and longer lead times can cap near-term market growth; LightCounting expects linear-drive solutions to weigh on DSP sales in 2027-2031; and Cisco's roadmap discussion highlights costly 2nm/3nm development and possible fragmentation among 1600ZR, 1600ZR+, and coherent-lite. Celero reports validated 2nm silicon and a 1.6T-to-3.2T path, but its financing is still directed partly to production readiness. Without disclosed volume shipments, design wins, ASPs, or qualification schedules, adoption timing and obtainable share remain unverified.[CM006, CM012, CM013, CM014, CM015, CM016]

2.5 Exhibits

3.1 Competitive landscape and buyer alternatives

The relevant market is not a single list of DSP vendors. Buyers can select short-reach PAM4 optics, longer-reach coherent pluggables, co-packaged optics, optical I/O chiplets, or internal silicon. CapitalG describes PAM4 as cost-effective but constrained at 1.6T and 3.2T+ by noise, degradation, and reach, while legacy coherent is capable over distance but too costly and power-hungry for broad data-center deployment. That framing makes Celero's direct competition a technology choice between incumbent architectures as much as a company-versus-company contest. LightCounting's February 2026 report lists Broadcom, Credo, MACOM, Marvell, MaxLinear, and Semtech among leading PAM4 suppliers, and separately profiles coherent suppliers including Cisco/Acacia, Ciena, Huawei, Nokia, ZTE, and smaller vendors such as Celero and Retym. The competitive set therefore includes scaled silicon vendors with qualification and distribution advantages, specialist coherent vendors, and adjacent optical-compute platforms. Celestial AI's $515 million cumulative funding and Photonic Fabric platform demonstrate that well-capitalized alternatives can attack the same AI bandwidth and latency problem from a different layer. UCIe also shows that open chiplet standards are a parallel ecosystem route for moving data closer to the package.[CP001, CP002, CP003, CP004]

3.2 Capability, scale, and positioning

Celero's differentiation is strongest at the architecture and team level, but the public record does not establish product revenue, named production customers, pricing, or design wins. CapitalG's November 2025 investment note says Celero was building coherent DSP platforms for AI-scale networking and describes a 100-person team with founders from Broadcom, Inphi, Marvell, and ClariPhy. Its later investor update reports an industry's first 2nm coherent DSP tape-out and an architecture intended to carry more data per link than traditional PAM4 with lower power than legacy coherent. Those are important technical milestones, but they remain investor-issued claims rather than independent deployment evidence. By contrast, Futurum reports Broadcom's 3nm Taurus BCM83640 sampling to early access customers and partners, with 400G/lane interfaces aimed at 1.6T modules and a roadmap toward 3.2T. Futurum also notes Marvell's Electra and Libra coherent portfolio and warns that NVIDIA's reported in-house DSP effort and co-packaged optics could compress the addressable market. The comparison is therefore asymmetric: Celero may offer a technically attractive middle path, but incumbents currently show stronger evidence of qualification readiness and ecosystem reach.[CP005, CP006, CP007, CP008]

3.3 Switching costs, ecosystem power, and moat durability

Switching costs in optical interconnects are created by silicon qualification, module interoperability, foundry and packaging access, software and standards compatibility, and the risk of redesigning a deployed topology. Futurum says transceiver qualification cycles are lengthy and that early DSP design wins can persist because module manufacturers are reluctant to re-engineer validated platforms. This favors Broadcom and Marvell if their sampling and standards positions translate into volume designs. Celero's claimed founder experience and foundry relationships could reduce execution risk, but no public source in this pool verifies customer contracts, production volumes, realized pricing, or the durability of those relationships. Ayar Labs illustrates another moat pattern: substantial financing is being used to expand manufacturing, test capacity, and ecosystem partnerships for co-packaged optics, while Celestial AI's large funding base supports an alternative optical fabric. The adverse case is thus not that Celero lacks technical differentiation; it is that architecture selection, incumbent distribution, internal silicon, or CPO could commoditize or bypass a standalone coherent-DSP layer before Celero reaches scale. A reasonable underwriting stance is to credit technical optionality while leaving commercial moat, pricing power, and customer lock-in as open questions.[CP009, CP010, CP011, CP012]

3.4 Competitive diligence implications

The evidence supports a focused diligence agenda rather than a definitive market-share conclusion. Celero should be tested against the actual buying criteria of hyperscalers and optical-module partners: bit rate and reach at system conditions, watts per bit, module bill of materials, standards interoperability, security features, qualification status, and time to volume. Public materials establish the architecture narrative and funding backdrop, but not the denominator needed to compare customer adoption or economics. The most decision-relevant missing evidence is a customer-backed design-win list, sampling and qualification milestones, unit pricing and gross-margin assumptions, and the share of deployments where coherent is required rather than merely advantageous. Until those are disclosed or independently corroborated, Celero's moat should be treated as conditional on execution and ecosystem conversion.[CP006, CP007, CP009, CP012]

3.5 Exhibits

4.1 Revenue model and monetization visibility

Celero's public materials describe a fabless semiconductor business selling coherent digital signal processor technology for optical interconnects in AI infrastructure. The revenue mechanism is therefore expected to be chip or platform sales into transceiver, networking, or infrastructure supply chains, but public evidence does not disclose contractual pricing, shipment volume, realized revenue, royalty terms, or revenue recognition policy. The company says its technology targets 1.6T through 3.2T connectivity and production readiness, while external analysis emphasizes that validated silicon is not the same as volume-shipped product. List-like technical claims should not be treated as ARR, revenue, or gross margin.[CI001, CI002, CI003, CI004]

4.2 Cost structure and unit economics

The economics are dominated by semiconductor development and commercialization rather than a disclosed recurring software subscription. Celero's roadmap requires advanced-node silicon, analog and DSP design, foundry access, testing, packaging, qualification, customer integration, and eventual production scale. CapitalG describes a 2nm tape-out and a purpose-built architecture, while market evidence shows that optical supply chains face upstream laser and capacity bottlenecks. Those facts support a potentially high-value component opportunity but do not establish wafer cost, gross margin, yield, inventory turns, warranty exposure, customer concentration, or CAC/payback. Every missing unit-economic field remains a diligence request rather than an estimate.[CI005, CI006, CI007, CI008]

4.3 Traction, financing dependency, and capital adequacy

Celero's disclosed capital base is meaningful relative to a two-year-old chip startup, but financing raised is not cash available and does not prove commercial traction. The November 2025 company release reported $140 million of total funding, including a $100 million Series B and $40 million of earlier rounds. September 2026 coverage reports a $275 million Series C at a valuation above $3 billion and about $415 million cumulatively, with the stated uses including roadmap acceleration, research and development, and production readiness. No public source in this pool supplies cash on hand, quarterly burn, runway, debt, working-capital needs, customer deposits, or design-win revenue. Capital adequacy therefore depends on tape-out-to-production execution and the timing of the next financing or commercial cash inflow.[CI009, CI010, CI011, CI012, CI013]

4.4 Financial verdict and underwriting blockers

The financial profile is best characterized as well funded but commercially unproven. The capital raise and investor participation reduce near-term financing uncertainty, while the absence of disclosed revenue, margin, cash, burn, pricing, and customer commitments prevents a conventional earnings or cash-flow underwriting. Supply constraints can create urgency and pricing power, but they can also raise input, qualification, and delivery risk. Broader semiconductor funding is concentrated in large rounds and remains exposed to continued AI infrastructure spending, so follow-on capital cannot be assumed. A credible underwriting package should require audited or management financials, current cash and burn, a product-level costed bill of materials, yield and capacity assumptions, signed customer or channel commitments, and evidence that the latest silicon has moved beyond validation into paid production deployments.[CI014, CI015, CI016]

4.5 Exhibits

5.1 Product and customer workflow

Celero sells a coherent digital signal processor platform rather than a complete data-center network. The disclosed workflow is to place signal-processing silicon inside optical interconnect hardware so electrical data from AI accelerators can be transported over fiber between racks, clusters, campuses, and data centers. The company describes the target problem as the bandwidth, reach, latency, power, and cost limits that emerge as AI systems connect increasing numbers of accelerators. SiliconANGLE independently reports that Celero is focused on short- and medium-reach optical links, where coherent optics had previously been viewed as too costly or power hungry, while the company describes its target as high-bandwidth, low-power connectivity. This is a credible problem definition, but the public record does not identify a production SKU, named customer deployment, measured power envelope, yield, or realized link economics. Those omissions matter because the product's value depends on system-level performance, not only on a DSP architecture claim.[CE001, CE002, CE003, CE004]

5.2 Architecture, operating model, and maturity

The architecture disclosed publicly has three functional layers: electrical data from accelerators is converted by a DSP, carried through coherent optical modulation over fiber, and managed as part of an interoperable optical module or network. CapitalG describes Celero as building coherent DSP platforms purpose-built for AI data centers and says the architecture is intended to carry more data per link than traditional PAM4 while using less power than legacy coherent approaches. The same investor source says Celero taped out 2nm coherent DSP silicon after its Series B, but this is an investor statement rather than an independent tape-out report or customer qualification record. OIF materials provide useful market context: current work spans 1600ZR, 1600ZR+, 1600CL, coherent module management, security for CMIS, and energy-efficient interfaces. That context supports the relevance of Celero's design direction, not Celero-specific compliance or interoperability. Public evidence therefore supports an advanced silicon-development stage, while production readiness, qualification, software/firmware controls, and manufacturing milestones remain unverified.[CE005, CE006, CE007, CE008]

5.3 Differentiation, trust, and implementation risk

Celero's strongest disclosed differentiator is the founders' prior experience shipping multiple generations of coherent DSP and networking IC products at Marvell, Inphi, Broadcom, and ClariPhy. The company also points to a purpose-built balance between telecom-grade coherent performance and data-center power and cost constraints. That combination is strategically relevant, but most detailed performance language is company- or investor-issued and is not accompanied by public benchmark methodology, independent test data, patents, certifications, security attestations, customer references, or incident history. OIF's active work on CMIS management, CMIS security, 1600G coherent interfaces, and energy-efficient interfaces shows that interoperability, management, security, and power are live engineering dependencies for the category. Celero's product-risk profile is consequently asymmetric: the technical thesis is coherent and founder credibility is strong, but the diligence case still depends on evidence of silicon bring-up, foundry and packaging execution, interoperability testing, secure module management, reliability qualification, and named production deployments.[CE010, CE011, CE012, CE013, CE014]

5.4 Product verdict and diligence priorities

The evidence supports a technically focused coherent-DSP platform aimed at a real AI-networking bottleneck, not a fully evidenced commercial product. Celero has disclosed its target workflow, a coherent-silicon architecture, a high-experience founding team, and financing sufficient to pursue engineering and commercialization. It has not publicly disclosed the metrics needed to underwrite product maturity: tape-out or sample dates by product, process and package details, measured link performance, power at stated rates, yield, qualification status, customer production status, support model, security controls, or failure-rate data. The appropriate product judgment is therefore promising but pre-scale and evidence constrained. The next diligence step should request independent lab results, qualification and reliability reports, design-win status by SKU, manufacturing and packaging dependencies, and a security/compliance evidence pack rather than extrapolating from funding or investor confidence.[CE015, CE016, CE017]

5.5 Exhibits

6.1 Target buyers, users, and deployment settings

Celero's stated route to market centers on two direct account types: hyperscalers and optical module makers. Its Marketing Director posting describes engineering executives and architects as the audience, asks the role to translate hyperscaler networking requirements into DSP specifications, and calls for early-stage design wins with both account types. The operating user is therefore likely a network, optical, or system engineering team, while the economic buyer and payer remain undisclosed. Celero's own release places the product across AI accelerator clusters and cloud data-center connections. Reuters narrows the use case to translating optical and electrical signals for links spanning data centers. OIF and AWS show a broader ecosystem of cloud operators, model developers, system vendors, and component suppliers, but neither establishes a commercial relationship with Celero.[CU001, CU002, CU003, CU004, CU005, CU006]

6.2 Adoption signals stop before customer deployment

The strongest public signals are product-readiness and commercialization milestones rather than customer outcomes. CapitalG says Celero taped out a 2nm coherent DSP and describes links scaling from 1.6T to 3.2T and beyond. The current job posting is more revealing for customer maturity: it asks a new commercial leader to build go-to-market plans and secure critical early-stage design wins. Reuters likewise says the company is designing its chip and plans to embed new algorithms, language that does not verify volume shipment. Celero's November 2025 release and its syndicated copy discuss market need and funding but disclose no customer count, shipment volume, production qualification, paid deployment, or design-win conversion. The retained corpus therefore supports a credible sales target and technical proposition, not proven customer adoption.[CU008, CU009, CU010, CU011, CU012, CU016]

6.3 Durability, expansion, and concentration remain private

Demand conditions are favorable but cannot substitute for company-level retention evidence. CoreWeave cites a Futurum survey in which 68% of 820 AI decision-makers were past experimentation, while OIF convened Microsoft, Google Cloud, Meta, OpenAI, system vendors, semiconductor suppliers, and standards bodies around 448Gbps signaling. Those facts indicate sophisticated prospective buyers and a large qualification ecosystem. A reasonable customer journey runs from requirements definition to design win, silicon and module qualification, paid production, and then repeat platform adoption. Only the early stages are visible for Celero. No assigned source supplies GRR, NRR, churn, contract duration, renewal, repeat-order, expansion-revenue, or customer-concentration data. These are material underwriting gaps, especially because a semiconductor startup may depend on a small number of long-cycle design wins before revenue diversifies.[CU007, CU013, CU014, CU015]

6.4 Exhibits

7.1 Ranked risk view

The highest-confidence risk is execution through commercialization: Celero publicly describes coherent DSP technology and a 2nm tape-out, but the retained evidence does not establish production shipments, customer design wins, qualification status, yield, or recurring revenue. That gap makes the downside asymmetric because semiconductor programs can consume substantial capital before customer acceptance. The second tier is external dependency: the product is an advanced semiconductor subject to export-control interpretation, foundry access, packaging, and supply continuity. A third tier is information risk. The company is private and its public materials emphasize technology and funding rather than operating metrics, so investors cannot independently test burn, margins, customer concentration, or incident history. These are evidence gaps, not proof that an incident or failure has occurred.[CR001, CR002, CR003, CR004]

7.2 Regulatory and legal exposure

Export controls are a material diligence item because Celero develops coherent DSP silicon for AI infrastructure and maintains design centers in Irvine, Canada, and Argentina. The Federal Register rule retained for this chapter is a Department of Commerce/BIS action covering advanced computing items, semiconductor end use, license requirements, and country-scope changes; it also includes a section titled “Need To Continuously Monitor the FDP Rules and revise license review Policies as Needed.” That does not show that Celero is restricted, but it does show a changing compliance perimeter for semiconductor businesses. The CHIPS for America page states that the 2022 law provided Commerce $50 billion, including $39 billion for facilities and equipment and $11 billion for research and development. Celero's access to incentives, suppliers, and cross-border engineering should therefore be checked against eligibility, end-use, ownership, and export-control procedures. Separately, trade-secret protection matters for a design-led company: the cited statute permits an owner of a trade secret used in interstate or foreign commerce to bring a civil action, but no public source in this pool confirms Celero's assignments, controls, or disputes.[CR005, CR006, CR007, CR008]

7.3 Operational, partner, and financial dependencies

Celero's operating model depends on turning a complex DSP design into qualified silicon and then into customer deployments. CapitalG describes a 2nm tape-out and says the architecture scales from 1.6T to 3.2T and beyond, while Celero's own materials describe high-bandwidth, low-power optical connectivity and a distributed design footprint. Those statements support technical ambition, not manufacturing yield, cost, warranty performance, or delivery reliability. The partner and supply-chain questions are consequently central: which foundry, packaging, test, optical-module, and cloud or systems partners are qualified; how many alternatives exist; and what happens if a node, mask, package, or component is delayed? Public funding disclosures also do not equal cash available. The company announced $140 million through November 2025, while the later CapitalG page describes a $275 million Series C; the pool does not provide terms, closing evidence, cash balance, burn, or valuation. Those unknowns increase financing and dilution risk.[CR009, CR010, CR011, CR012]

7.4 Mitigations, monitoring, and thesis breaks

The practical mitigation is a milestone-based underwriting plan rather than reliance on investor or company confidence. Before increasing exposure, request independent evidence of tape-out completion, wafer acceptance, production qualification, named design wins, shipment volume, gross margin, and customer-funded or partner-funded commitments. Monitor export classifications and licenses by destination and end use, foundry and packaging lead times, yield and return rates, cash runway, hiring by function, and concentration in any one customer or supplier. The thesis should break if the next planned silicon milestone slips materially, if qualification fails without a credible re-spin plan, if export approvals or customer deployments are blocked, or if financing requires a down round before commercial traction is demonstrated. Absence of a public breach, lawsuit, or outage in the assigned sources should remain an unresolved diligence question rather than a clean bill of health.[CR013, CR014]

7.5 Exhibits

8.1 Investment case and anti-thesis

The positive case is that Celero has moved from a funded technical thesis toward production readiness. The September 2026 financing announcement says the company raised $275 million in Series C, brought total capital to $415 million, and validated what it calls the industry's first 2nm coherent DSP silicon. CapitalG, which led the earlier Series B and co-led the Series C, describes a 1.6T-to-3.2T architecture and says the team taped out the silicon. These are credible signals of investor conviction and technical progress, but they are not customer revenue, shipment volume, gross margin, or independently verified design wins. The anti-thesis is therefore commercialization risk: a large round can fund a long tape-out-to-production cycle, while the public evidence does not establish adoption, pricing, yield, or a payback period for customers.[CV001, CV002, CV003, CV004, CV005]

8.2 Financing context and price discipline

The financing record has strengthened materially since the prior disclosed round. Celero's November 2025 release described a $100 million Series B and $140 million of cumulative funding; the September 2026 announcement reports a $275 million Series C, $415 million cumulative capital, and a valuation above $3 billion. The latter is the only current public valuation mark in the assigned evidence, and it is company-reported through a syndicated release rather than a term sheet or audited filing. It is not possible to calculate a revenue multiple, ARR multiple, dilution burden, liquidation preference, or investor return from the retained public text. Public semiconductor comparables show why scale and margin matter: an AInvest article describes Marvell as trading at roughly 31x sales and warns that a high-growth optical thesis depends on execution and supply-chain constraints, while a Trefis comparison shows Broadcom's much larger revenue and margin base. Those are contextual benchmarks, not direct Celero valuation comparables, so the appropriate discipline is to condition entry on verified revenue, margins, customer commitments, and financing terms.[CV006, CV007, CV008, CV009, CV010]

8.3 Scenarios, recommendation, and diligence

A bull case requires the 2nm platform to convert into production shipments across the stated 1.6T-to-3.2T range, with repeatable yields, named or verifiable hyperscale design wins, and enough gross margin to justify the company-reported valuation. The base case is continued technical progress and additional financing while commercial proof remains private, which supports tracking rather than underwriting a return. The bear case is delayed qualification, weak yields, customer concentration, or an optical supply-chain bottleneck that shifts value to adjacent component suppliers; the independent AInvest review explicitly says the bottleneck may be EML lasers and indium-phosphide substrates rather than DSP design. Since no retained source supplies Celero revenue, ARR, margin, customer count, preference stack, or exit timing, the recommendation is research-more. The thesis breaks if management cannot provide production qualification, unit economics, customer commitments, and a clean capitalization schedule.[CV011, CV012, CV013, CV014, CV015, CV016]

8.4 Exhibits